- 12 Apr, 2024 15 commits
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Aric Cyr authored
This version brings along the following: - DCN10 fixes - DCN316 fixes - DML2 fixes - DWB fixes - Expanded FAMS support - Misc code style fixes - ODM fixes - VSC SDP fixes Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rodrigo Siqueira authored
This commit makes some small adjustments in the dwb header. Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Felix Kuehling authored
Fix memory leak due to a leaked mmget reference on an error handling code path that is triggered when attempting to create KFD processes while a GPU reset is in progress. Fixes: 0ab2d753 ("drm/amdkfd: prepare per-process debug enable and disable") CC: Xiaogang Chen <xiaogang.chen@amd.com> Signed-off-by:
Felix Kuehling <felix.kuehling@amd.com> Tested-by:
Harish Kasiviswanthan <Harish.Kasiviswanthan@amd.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Change DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT with DP_PHY_REPEATER_128B132B_RATES. Acked-by:
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Rodrigo Siqueira authored
Set OTG/OPTC parameters to 0 if something goes wrong on DCN10. Acked-by:
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Rodrigo Siqueira authored
Set OTG/OPTC parameter to 0 if failed to set DRR. Acked-by:
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Rodrigo Siqueira authored
Update DCN10 to use legacy fast update and ensure that the MPCC count is the same as the pipe_count. Acked-by:
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Rodrigo Siqueira authored
[WHY] DCN 1.0 is not ready for the P010 support. [HOW] 1. Set the P010 plan_cap of DCN 1.0 to be false. 2. Let the DM do the plan cap initialization of DCN 1.0. Reviewed-by:
Figo Wang <shen-hong.wang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Some of the resource capabilities for DCN201 and the debug default option are outdated. This commit just set some of the missing configurations for DCN201. Acked-by:
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Rodrigo Siqueira authored
This commit removes code that are not used by display anymore. Acked-by:
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Rodrigo Siqueira authored
Some of the includes used in the DC can be removed and others need to be update. This commit adjusts some of those headers in the display code. Acked-by:
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Rodrigo Siqueira authored
This commit just introduce some basic comments that helps to understand the overall behavior of some structs. Acked-by:
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Christian König authored
The majority of those where removed in the commit aed01a68 ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") But this one was missed because it's working on the resource and not the BO. Since we also no longer use a fake start address for visible BOs this will now trigger invalid mapping errors. v2: also remove the unused variable Signed-off-by:
Christian König <christian.koenig@amd.com> Fixes: aed01a68 ("drm/amdgpu: Remove TTM resource->start visible VRAM condition v2") CC: stable@vger.kernel.org Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Jack Xiao authored
Set SDMAx_WATCHDOG_CNTL.QUEUE_HANG_COUNT registers to improve SDMA reliability. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Luqmaan Irshad authored
Adding a new field for GPU Capacity to align the header with the host. Signed-off-by:
Luqmaan Irshad <Luqmaan.Irshad@amd.com> Acked-by:
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- 10 Apr, 2024 25 commits
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Yifan Zhang authored
This patch to differentiate external rev id for gfx 11.5.0. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Xiang Yang authored
the dram_clock_change_latency_us in dcn3_51_soc is initialized twice, so delete one of them. Acked-by:
Xiang Yang <xiangyang3@huawei.com> Signed-off-by:
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Simon Horman authored
The path to GPU documentation is Documentation/gpu rather than Documentation/GPU This appears to have been introduced by commit ba162ae7 ("Documentation/gpu: Introduce a simple contribution list for display code") Flagged by make htmldocs. Signed-off-by:
Simon Horman <horms@kernel.org> Signed-off-by:
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Erick Archer authored
This is an effort to get rid of all multiplications from allocation functions in order to prevent integer overflows [1] [2]. In this case, the memory allocated to store RADEONFB_CONN_LIMIT pointers to "drm_connector" structures can be avoided. This is because this memory area is never accessed. Also, in the kzalloc function, it is preferred to use sizeof(*pointer) instead of sizeof(type) due to the type of the variable can change and one needs not change the former (unlike the latter). At the same time take advantage to remove the "#if 0" block, the code where the removed memory area was accessed, and the RADEONFB_CONN_LIMIT constant due to now is never used. Link: https://www.kernel.org/doc/html/latest/process/deprecated.html#open-coded-arithmetic-in-allocator-arguments [1] Link: https://github.com/KSPP/linux/issues/160 [2] Acked-by:
Erick Archer <erick.archer@outlook.com> Signed-off-by:
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Rodrigo Siqueira authored
DCN10 OPTC is used by other DCNs, and in some cases it might be useful to have V_TOTAL_REGS available. This commit add V_TOTAL_REGS as part of the TG field. Acked-by:
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Anthony Koo authored
- Add boot option to change the ONO powerup flow, impacting the order of power domains to power up or down first Acked-by:
Anthony Koo <anthony.koo@amd.com> Signed-off-by:
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Qili Lu authored
This reverts commit b72a7e0f. It causes a dead loop in dml_prefetch_check. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Qili Lu <qili.lu@amd.com> Signed-off-by:
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George Shen authored
[Why] For video mode test pattern (i.e. test pattern disable), the call to rebuild test pattern params for the pipe is skipped. This causes dynamic disablement of test pattern to not work, as the test_pattern_params of the pipe will not be updated and retain the values of the previously enabled test pattern. [How] Rebuild test pattern params even when test pattern is video mode, allowing the pipe to have updated test_pattern_params values. Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
George Shen <george.shen@amd.com> Signed-off-by:
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Zhongwei authored
[Why] OLED panels show no display for large vtotal timings. [How] Check if ss is enabled and read from lut for spread spectrum percentage. Adjust dprefclk as required. DP_DTO adjustment is for edp only. Cc: stable@vger.kernel.org Reviewed-by:
Zhongwei <zhongwei.zhang@amd.com> Signed-off-by:
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Harry Wentland authored
The previous check for the is_vsc_sdp_colorimetry_supported flag for MST sink signals did nothing. Simplify the code and use the same check for MST and SST. Cc: stable@vger.kernel.org Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Harry Wentland authored
In order for display colorimetry to work correctly on DP displays we need to send the VSC SDP packet. We should only do so for panels with DPCD revision greater or equal to 1.4 as older receivers might have problems with it. Cc: stable@vger.kernel.org Cc: Joshua Ashton <joshua@froggi.es> Cc: Xaver Hugl <xaver.hugl@gmail.com> Cc: Melissa Wen <mwen@igalia.com> Cc: Agustin Gutierrez <Agustin.Gutierrez@amd.com> Reviewed-by:
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Charlene Liu authored
[why] dwb was not POR previosly. now need to enable dwb in dml2. Limitation: HW DML assumes only one DWB one set of watermark for all 4 watermark sets one stream has one DWB only. WB scaling dml input has one set of scaling tap. (no chroma so far) needs to follow up Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
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Parandhaman K authored
why and how: as part of cleanup, need to refactor vpg. It was improperly referenced as a dcn specfic part of link. the dcn agnostic code needed was ripped out and put into vpg.h, now in dc/inc/hw. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Parandhaman K <parandhaman.k@amd.com> Signed-off-by:
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Allen Pan authored
[Why] 6.75 Gbps link rate training for DP_TEST_LINK_RATE_RATE_8 Reviewed-by:
Allen Pan <allen.pan@amd.com> Signed-off-by:
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Fudongwang authored
[Why] Wrong logic cause screen corruption. [How] Port logic from DCN35/314. Cc: stable@vger.kernel.org Reviewed-by:
Fudongwang <fudong.wang@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW] We should not be recursively calling the manual trigger programming function when FAMS is not in use. Cc: stable@vger.kernel.org Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Dillon Varone authored
[WHY&HOW] Changes to support future versions of FAMS. Reviewed-by:
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Lijo Lazar authored
Setting soft max frequency for MCLK is allowed in 1VF mode in SMUv13.0.6 SOCs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] When Subvp pipe's index is smaller than main pipe's index, the main pipe's ODM policy is not yet assigned. If we assign subvp pipe's ODM policy based on main pipe, we will assign uninitialized ODM policy. [how] Instead of copying main pipe's policy we copy the main pipe ODM policy logic. So it doesn't matter whether if main pipe's ODM policy is set, phantom pipe will always have the same policy because it running the same calcualtion to derive ODM policy. Cc: stable@vger.kernel.org Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] In current implemenation ODM mode is only reset when the last plane is removed from dc state. For any dc validate we will always remove all current planes and add new planes. However when switching from no planes to 1 plane, ODM mode is not reset because no planes get removed. This has caused an issue where we kept ODM combine when it should have been remove when a plane is added. The change is to reset ODM mode when adding the first plane. Cc: stable@vger.kernel.org Reviewed-by:
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Tim Huang authored
The RB bitmap should be global active RB bitmap & active RB bitmap based on active SA. Signed-off-by:
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Alex Hung authored
mode_config's max width x height is 4096x2160 and is higher than DWB's max resolution 3840x2160 which is returned instead. Cc: stable@vger.kernel.org Reviewed-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Lewis Huang authored
[Why] We want flexibility to choose how pwrseq instance is mapped to eDP panel [How] Add configuration option to choose the pwrseq mapping policy. When enabled, allow fixed mapping between DIG inst to pwrseq inst. Reviewed-by:
Lewis Huang <lewis.huang@amd.com> Signed-off-by:
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Zhigang Luo authored
1. change AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT from 30 to 5. 2. set fatel error detected flag. Signed-off-by:
Zhigang Luo <Zhigang.Luo@amd.com> Reviewed-by:
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Zhigang Luo authored
If there are more than one device doing reset in parallel, the first device will call kfd_suspend_all_processes() to evict all processes on all devices, this call takes time to finish. other device will start reset and recover without waiting. if the process has not been evicted before doing recover, it will be restored, then caused page fault. Signed-off-by:
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