- 11 Sep, 2018 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-2018-09-06-2' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Merge tag 'gvt-next-2018-09-04' drm-intel-next-2018-09-06-1: UAPI Changes: - GGTT coherency GETPARAM: GGTT has turned out to be non-coherent for some platforms, which we've failed to communicate to userspace so far. SNA was modified to do extra flushing on non-coherent GGTT access, while Mesa will mitigate by always requiring WC mapping (which is non-coherent anyway). - Neuter Resource Streamer uAPI: There never really were users for the feature, so neuter it while keeping the interface bits for compatibility. This is a long due item from past. Cross-subsystem Changes: - Backmerge of branch drm-next-4.19 for DP_DPCD_REV_14 changes Core Changes: - None Driver Changes: - A load of Icelake (ICL) enabling patches (Paulo, Manasi) - Enabled full PPGTT for IVB,VLV and HSW (Chris) - Bugzilla #107113: Distribute DDB based on display resolutions (Mahesh) - Bugzillas #100023,#107476,#94921: Support limited range DP displays (Jani) - Bugzilla #107503: Increase LSPCON timeout (Fredrik) - Avoid boosting GPU due to an occasional stall in interactive workloads (Chris) - Apply GGTT coherency W/A only for affected systems instead of all (Chris) - Fix for infinite link training loop for faulty USB-C MST hubs (Nathan) - Keep KMS functional on Gen4 and earlier when GPU is wedged (Chris) - Stop holding ppGTT reference from closed VMAs (Chris) - Clear error registers after error capture (Lionel) - Various Icelake fixes (Anusha, Jyoti, Ville, Tvrtko) - Add missing Coffeelake (CFL) PCI IDs (Rodrigo) - Flush execlists tasklet directly from reset-finish (Chris) - Fix LPE audio runtime PM (Chris) - Fix detection of out of range surface positions (GLK/CNL) (Ville) - Remove wait-for-idle for PSR2 (Dhinakaran) - Power down existing display hardware resources when display is disabled (Chris) - Don't allow runtime power management if RC6 doesn't exist (Chris) - Add debugging checks for runtime power management paths (Imre) - Increase symmetry in display power init/fini paths (Imre) - Isolate GVT specific macros from i915_reg.h (Lucas) - Increase symmetry in power management enable/disable paths (Chris) - Increase IP disable timeout to 100 ms to avoid DRM_ERROR (Imre) - Fix memory leak from HDMI HDCP write function (Brian, Rodrigo) - Reject Y/Yf tiling on interlaced modes (Ville) - Use a cached mapping for the physical HWS on older gens (Chris) - Force slow path of writing relocations to buffer if unable to write to userspace (Chris) - Do a full device reset after being wedged (Chris) - Keep forcewake counts over reset (in case of debugfs user) (Imre, Chris) - Avoid false-positive errors from power wells during init (Imre) - Reset engines forcibly in exchange of declaring whole device wedged (Mika) - Reduce context HW ID lifetime in preparation for Icelake (Chris) - Attempt to recover from module load failures (Chris) - Keep select interrupts over a reset to avoid missing/losing them (Chris) - GuC submission backend improvements (Jakub) - Terminate context images with BB_END (Chris, Lionel) - Make GCC evaluate GGTT view struct size assertions again (Ville) - Add selftest to exercise suspend/hibernate code-paths for GEM (Chris) - Use a full emulation of a user ppgtt context in selftests (Chris) - Exercise resetting in the middle of a wait-on-fence in selftests (Chris) - Fix coherency issues on selftests for Baytrail (Chris) - Various other GEM fixes / self-test updates (Chris, Matt) - GuC doorbell self-tests (Daniele) - PSR mode control through debugfs for IGTs (Maarten) - Degrade expected WM latency errors to DRM_DEBUG_KMS (Chris) - Cope with errors better in MST link training (Dhinakaran) - Fix WARN on KBL external displays (Azhar) - Power well code cleanups (Imre) - Fixes to PSR debugging (Dhinakaran) - Make forcewake errors louder for easier catching in CI (WARNs) (Chris) - Fortify tiling code against programmer errors (Chris) - Bunch of fixes for CI exposed corner cases (multiple authors, mostly Chris) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180907105446.GA22860@jlahtine-desk.ger.corp.intel.com
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- 07 Sep, 2018 2 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linuxDave Airlie authored
omapdrm changes for v4.20 Big amount of changes from Laurent, reworking the driver towards the model used by the other DRM drivers by reverting the direction of many of the operations on the display pipeline. The aim of this work is to allow omapdrm to use the common DRM panels and bridges. Not all of the operations are dealt in these patches, so more work needs to be done. The only change visible to the user should be the change in module dependencies: e.g. earlier a panel module depended on an encoder module, but now the encoder module depends on the panel module, which affects the order in which to unload the modules. Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-miscDave Airlie authored
drm-misc-next for 4.20: UAPI Changes: - Add userspace dma-buf device to turn memfd regions into dma-bufs (Gerd) - Add per-plane blend mode property (Lowry) - Change in drm_fourcc.h is documentation only (Brian) Cross-subsystem Changes: - None Core Changes: - Remove user logspam and useless lock in vma_offset_mgr destroy (Chris) - Add get/verify_crc_source for improved crc source selection (Mahesh) - Add __drm_atomic_helper_plane_reset to reduce copypasta (Alexandru) Driver Changes: - various: Replance ref/unref calls with drm_dev_get/put (Thomas) - bridge: Add driver for TI SN65DSI86 chip (Sandeep) - rockchip: Add PX30 support (Sandy) - sun4i: Add support for R40 TCON (Jernej) - vkms: Continued building out vkms, added gem support (Haneen)Driver Changes: - various: fbdev: Wrap remove_conflicting_framebuffers with resource_len accessors to remove a bunch of cargo-cult (Michał) - rockchip: Add rgb output iface support + fixes (Sandy/Heiko) - nouveau/amdgpu: Add cec-over-aux support (Hans) - sun4i: Add support for Allwinner A64 (Jagan) Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Mirosław <mirq-linux@rere.qmqm.pl> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Sandy Huang <hjc@rock-chips.com> Cc: Hans Verkuil <hans.verkuil@cisco.com> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by:
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- 06 Sep, 2018 4 commits
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Joonas Lahtinen authored
Signed-off-by:Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
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https://github.com/intel/gvt-linuxJoonas Lahtinen authored
gvt-next-2018-09-04 - guest context shadow optimization for restore inhibit one (Yan) - cmd parser optimization (Yan) - W=1 warning fixes (Zhenyu) Signed-off-by:
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Joonas Lahtinen authored
Signed-off-by: -
Joonas Lahtinen authored
Signed-off-by:
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- 05 Sep, 2018 21 commits
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Chris Wilson authored
Introduce a complementary function to i915_driver_create() to undo all that is created. Suggested-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
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Chris Wilson authored
Attach our device_info to the our i915 private on creation so that it is always available for inspection. Signed-off-by:
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Heiko Stuebner authored
The newly added internal rgb encoder for Rockchip vops is missing stubs for the case that the rgb output part is not enabled in the kernel config. So add these. Fixes: 1f0f0151 (drm/rockchip: Add support for Rockchip Soc RGB output interface) Reviewed-by:
Sean Paul <seanpaul@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> [seanpaul fixed up checkpatch nits] Signed-off-by:
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Imre Deak authored
During IPS disabling the current 42ms timeout value leads to occasional timeouts, increase it to 100ms which seems to get rid of the problem. References: https://bugs.freedesktop.org/show_bug.cgi?id=107494 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107562Reported-by:
Diego Viola <diego.viola@gmail.com> Tested-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180905100005.7663-1-imre.deak@intel.com
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Haneen Mohammed authored
crtc_state is accessed by both vblank_handle() and the ordered work_struct handle vkms_crc_work_handle() to retrieve and or update the frame number for computed CRC. Since work_struct can fail, add frame_end to account for missing frame numbers. Use (frame_[start/end]) for synchronization between hrtimer callback and ordered work_struct handle. This patch passes the following subtests from igt kms_pipe_crc_basic test: bad-source, read-crc-pipe-A, read-crc-pipe-A-frame-sequence, nonblocking-crc-pipe-A, nonblocking-crc-pipe-A-frame-sequence Signed-off-by:
Haneen Mohammed <hamohammed.sa@gmail.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20180903211743.GA2773@haneenDRM
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Chris Wilson authored
Future gen reduce the number of bits we will have available to differentiate between contexts, so reduce the lifetime of the ID assignment from that of the context to its current active cycle (i.e. only while it is pinned for use by the HW, will it have a constant ID). This means that instead of a max of 2k allocated contexts (worst case before fun with bit twiddling), we instead have a limit of 2k in flight contexts (minus a few that have been pinned by the kernel or by perf). To reduce the number of contexts id we require, we allocate a context id on first and mark it as pinned for as long as the GEM context itself is, that is we keep it pinned it while active on each engine. If we exhaust our context id space, then we try to reclaim an id from an idle context. In the extreme case where all context ids are pinned by active contexts, we force the system to idle in order to recover ids. We cannot reduce the scope of an HW-ID to an engine (allowing the same gem_context to have different ids on each engine) as in the future we will need to preassign an id before we know which engine the context is being executed on. v2: Improved commentary (Tvrtko) [I tried at least] References: https://bugs.freedesktop.org/show_bug.cgi?id=107788Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180904153117.3907-1-chris@chris-wilson.co.uk
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Heiko Stuebner authored
The rk3188 has 2 vops not using iommus which only output directly to a rgb interface per vop. So all other output modes like hdmi are provided by external brige chips. Signed-off-by:
Sandy Huang <hjc@rock-chips.com> Acked-by:
Rob Herring <robh@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180830110937.1739-1-heiko@sntech.de
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Sandy Huang authored
Add this feature bit indicate px30 vop can directly output parallel or serial rgb data. Signed-off-by:
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Sandy Huang authored
Some Rockchip CRTCs, like rv1108 and px30, can directly output parallel and serial RGB data to panel or conversion chip. So add a feature-bit for vops to mark the ability for these direct outputs and add an internal encoder in that case, that can attach to bridge chipsor panels. Changes in v7: 1. forget to delete rockchip_rgb_driver and delete it. Changes in v6: 1. Update according to Heiko Stuebner' implemention, rgb output is part of vop's feature, should not register as a independent driver. Changes in v5: 1. add SPDX-License-Identifier tag Changes in v4: 1. add support px30; Changes in v3: 1. update for rgb-mode move to panel node. Changes in v2: 1. add error log when probe failed; 2. update name_to_output_mode() according to sean's suggest; 3. Fix uninitialized use of ret. Signed-off-by: -
Heiko Stuebner authored
To be able to have both internal subdrivers and external bridge drivers as output endpoints of vops, add a function to be able to distinguish these. changes in v8: - improved function documentation - better error handling - put calls for node and pdev references changes in v6: - added function to check subdriver vs. bridge Signed-off-by:
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Jernej Skrabec authored
Some boards have HDMI VCC pin connected to voltage regulator which may not be turned on by default. Add support for such boards by adding voltage regulator handling code to HDMI driver. Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net> [Icenowy: change supply name to "hvcc"] Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180904044053.15425-11-icenowy@aosc.io
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Icenowy Zheng authored
Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC" pin, which is the VCC of HDMI part. Add a supply property to specify HVCC's regulator in the device tree. Signed-off-by:
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Jagan Teki authored
The HDMI controller on Allwinner A64 is similar on the one on H3/H5/A83T (although the PHY is different with A83T). Add A64 compatible and append A83T compatible as fallback. Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Reviewed-by:
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Jagan Teki authored
Display Engine(DE2) in Allwinner A64 has two mixers and tcons. The routing for mixer0 is through tcon0 and connected to LVDS/RGB/MIPI-DSI controller. The routing for mixer1 is through tcon1 and connected to HDMI. Signed-off-by:
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Jagan Teki authored
Mixers in Allwinner have similar capabilities as others SoCs with DE2. Add support for them. Signed-off-by:
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Jagan Teki authored
Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the ones in A83T, but the mixers are new (similar to the later R40 SoC). This patch adds dt-binding documentation for A64 DE2 display pipeline. Signed-off-by:
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Gustavo A. R. Silva authored
There is a potential execution path in which pointer memfd is NULL when passed as argument to fput(), hence there is a NULL pointer dereference in fput(). Fix this by null checking *memfd* before calling fput(). Addresses-Coverity-ID: 1473174 ("Explicit null dereferenced") Fixes: fbb0de79 ("Add udmabuf misc device") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Link: http://patchwork.freedesktop.org/patch/msgid/20180904190749.GA9308@embeddedor.comSigned-off-by:
Gerd Hoffmann <kraxel@redhat.com>
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Gerd Hoffmann authored
Use the dma mapping api and properly add iommu mappings for objects, unless virtio is in iommu quirk mode. Signed-off-by:
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Gerd Hoffmann authored
The new function balances virtio_gpu_object_attach(). Also make virtio_gpu_cmd_resource_inval_backing() static and switch call sites to the new virtio_gpu_object_attach() function. Signed-off-by:
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Gerd Hoffmann authored
Track whenever an virtual output (crtc) is enabled or disabled. On atomic updates check for both framebuffer being present and crtc being enabled to figure whenever the output is active or not. Signed-off-by:
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Peter Wu authored
"crtc->helper_private" is not initialized by the QXL driver and thus the "crtc_funcs->disable" call would crash (resulting in suspend failure). Fix this by converting the suspend/resume functions to use the drm_mode_config_helper_* helpers. Tested system sleep with QEMU 3.0 using "echo mem > /sys/power/state". During suspend the following message is visible from QEMU: spice/server/display-channel.c:2425:display_channel_validate_surface: canvas address is 0x7fd05da68308 for 0 (and is NULL) spice/server/display-channel.c:2426:display_channel_validate_surface: failed on 0 This seems to be triggered by QXL_IO_NOTIFY_CMD after QXL_IO_DESTROY_PRIMARY_ASYNC, but aside from the warning things still seem to work (tested with both the GTK and -spice options). Signed-off-by:Peter Wu <peter@lekensteyn.nl> Link: http://patchwork.freedesktop.org/patch/msgid/20180904202747.14968-1-peter@lekensteyn.nlSigned-off-by:
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- 04 Sep, 2018 9 commits
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Chris Wilson authored
If the previous modeset commit has completed and is no longer part of the crtc state, skip waiting for it. Ville pointed out that, in fact, the commit is never removed after a modeset so the only way we could see a NULL here should be if there was never a commit attached. Nevertheless, we have the evidence it can be NULL and it has been defended against elsewhere, for example commit 93313538 ("drm/i915: Pass idle crtc_state to intel_dp_sink_crc"). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107792 Fixes: c44301fc ("drm/i915: Allow control of PSR at runtime through debugfs, v6") Signed-off-by:
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Chris Wilson authored
Using a spinlock to serialize the destroy function, within the destroy function itself does not prevent the buggy driver from shooting themselves in the foot - either way they still have a use-after-free issue. Reported-by:
Jia-Ju Bai <baijiaju1990@gmail.com> Signed-off-by:
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Chris Wilson authored
The ioctl arguments are under control of the user and as such we should resist any temptation to flood the kernel logs with their errors. Relegate the DRM_ERROR to a DRM_DEBUG so the user has to opt into hearing of their own mistakes. (One day we will have a small ringbuffer attached to the task, so that the concerned process can inspect its own debug info for EINVAL without them being hitting syslog at all.) Signed-off-by:
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Chris Wilson authored
Elsewhere we manipulate uncore.unclaimed_mmio_check and i915_param.mmio_debug under the irq lock (e.g. preserving the current value across a user forcewake grab), but do not protect the manipulation inside intel_uncore_arm_unclaimed_mmio_detection() from concurrent access, even from itself. This is an issue as we do call arm_unclaimed_mmio_detection from multiple threads without coordination. Suggested-by:
Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intelcom> Link: https://patchwork.freedesktop.org/patch/msgid/20180904131207.17563-1-chris@chris-wilson.co.uk
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Tvrtko Ursulin authored
There are two issues with the current RPCS programming for Icelake: Expansion of the slice count bitfield has been missed, as well as the required programming workaround for the subslice count bitfield size limitation. 1) Bitfield width for configuring the active slice count has grown so we need to program the GEN8_R_PWR_CLK_STATE accordingly. Current code was always requesting eight times the number of slices (due writing to a bitfield starting three bits higher than it should). These requests were luckily a) capped by the hardware to the available number of slices, and b) we haven't yet exported the code to ask for reduced slice configurations. Due both of the above there was no impact from this incorrect programming but we should still fix it. 2) Due subslice count bitfield being only three bits wide and furthermore capped to a maximum documented value of four, special programming workaround is needed to enable more than four subslices. With this programming driver has to consider the GT configuration as 2x4x8, while the hardware internally translates this to 1x8x8. A limitation stemming from this is that either a subslice count between one and four can be selected, or a subslice count equaling the total number of subslices in all selected slices. In other words, odd subslice counts greater than four are impossible, as are odd subslice counts greater than a single slice subslice count. This also had no impact in the current code base due breakage from 1) always reqesting more than one slice. While fixing this we also add some asserts to flag up any future bitfield overflows. v2: * Use a local in all branches for clarity. (Lionel) Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: tony.ye@intel.com Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
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Chris Wilson authored
Continuing the fun of trying to find exactly the delay that is sufficient to ensure that the page directory is fully loaded between context switches, move the extra flush added in commit 70b73f9a ("drm/i915/ringbuffer: Delay after invalidating gen6+ xcs") to just after we flush the pd. Entirely based on the empirical data of running failing tests in a loop until we survive a day (before the mtbf is 10-30 minutes). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107769 References: 70b73f9a ("drm/i915/ringbuffer: Delay after invalidating gen6+ xcs") Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180904063802.13880-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Currently, if the user has enabled mmio-debug around each register access, we presume that we have then checked them all. However, it is still possible through omission (raw register access) or external interaction that the unclaimed access was not highlighted. Signed-off-by:
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Ville Syrjälä authored
Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll mgr into the clock readout function as well. v2: Refactor the code into a common function s/is_icl/gen11+/ (Rodrigo) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com>
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Souptick Joarder authored
We have introduce new return type vm_fault_t for fault handler. Update the document for the same. Signed-off-by:
Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by:
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- 03 Sep, 2018 3 commits
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Chris Wilson authored
Older gen use a physical address for the hardware status page, for which we use cache-coherent writes. As the writes are into the cpu cache, we use a normal WB mapped page to read the HWS, used for our seqno tracking. Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm, which so far have not reoccurred with this patch. How reliable that evidence is remains to be seen. v2: Explicitly pass the expected physical address to the hw v3: Also remember the wild writes we once had for HWS above 4G. Signed-off-by:
Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20180903152304.31589-2-chris@chris-wilson.co.uk
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Chris Wilson authored
Pull the physical status page cleanup into a common cleanup_status_page() for caller simplicity. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180903152304.31589-1-chris@chris-wilson.co.uk
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Chris Wilson authored
We currently assert that if the target is in a CPU write domain, we use a CPU reloc path rather than the GPU reloc path. However, we have a debug override to force the GPU path and that unfortunately hits the assert. Include the async clflush under the debug option to ensure correct behaviour even when debugging, and strict when not. Signed-off-by:
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