- 10 Apr, 2024 40 commits
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Ma Jun authored
Add support for MACO flag checking. MACO mode only works if BACO is supported. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Ma Jun authored
Use a unified and more explicit name get_bamaco_support to replace is_baco_support and get_asic_baco_capability Signed-off-by:
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Ma Jun authored
Add a new runtime pm mode AMDGPU_RUNPM_BAMACO and related macro definition Signed-off-by:
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Kenneth Feng authored
fix the high voltage issue after unload on smu 13.0.10 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
This commit clean up some of the includes used by DCN. Signed-off-by:
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Rodrigo Siqueira authored
This commit adds some comments to make easier to understand the clock update for DCN 201, the encode function, and other minor comments. Signed-off-by:
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Rodrigo Siqueira authored
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Eric Bernstein authored
[Why] DTN only logs 'pipe_count' instances of MPCC. However in some cases there are different number of MPCC than DPP (pipe_count). [How] Add mpcc_count parameter to resource_pool and set it during pool construction and use it for DTN logging of MPCC state. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
This commit drops the RESERVE0 and RESERVE1 since both of them can be summarized as RESERVED. Signed-off-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
Adjust bytes per pixel calculation to use div_u64. Signed-off-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
Set alpha_en to 0 in some specific color formats. Signed-off-by:
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Rodrigo Siqueira authored
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Aric Cyr authored
This version pairs with DMUB FW Release 0.0.211.0 for dcn314, dcn35, dcn351 and brings along the following: - Fix underflow in subvp/non-subvp configs - Fix compiler warnings - Add handling for DC power mode - Add extra logging for DMUB, HUBP and OTG - Add timing pixel encoding for mst mode validation - Expand supported Replay residency mode - Allow HPO PG and RCG for DCN35 - Update pipe topology log to support subvp - Disable Z8 minimum stutter period check for DCN35 - Enable RCO for HDMISTREAMCLK in DCN35 Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Roman Li authored
[Why] We want to block IPS2 for static screen but allow it for power state transitions. [How] Set DalDisableIPS=6 for DCN35 which allows: 1. RCG during static screen 2. RCG during LVP 3. IPS2 for display off / S0i3 Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Aric Cyr authored
[why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially critical issues. [how] Fix all compiler warnings found with various compilers and higher warning levels. Primarily, potentially uninitialized variables and unreachable code. Reviewed-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
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Wenjing Liu authored
[why] Move built test pattern as part of pipe resource update for odm to ensure we rebuild test pattern params every time we have an ODM update Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Joshua Aberback authored
[Why] Future implementations will require a distinction between AC power and DC power (wall power and battery power, respectively). To accomplish this, adding a power mode parameter to certain dc interfaces, and adding a separate DML2 instance for DC mode validation. Default behaviour unchanged. Reviewed-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
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Joshua Aberback authored
[Why] When the DML2 wrapper explicitly accesses context->dml2, that creates a dependency on where dc saves the DML object. This dependency makes it harder to have multiple co-existing DML objects, which we would like to have for upcoming functionality. [How] - make all DML21 interfaces take in a DML2 object as parameter - remove all references to context->dml2, use parameter instead Reviewed-by:
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Alvin Lee authored
[Description] - Add logging for first DMUB inbox message that timed out to diagnostic data - It is useful to track the first failed message for debug purposes because once DMUB becomes hung (typically on a message), it will remain hung and all subsequent messages. In these cases we're interested in knowing which is the first message that failed. Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Xi (Alex) Liu authored
[Why and how] External display has corruption because no root clock control function. Add the function pointer to fix the issue. Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Reviewed-by:
Xi (Alex) Liu <xi.liu@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The threshold is no longer useful for blocking suboptimal power states for DCN35 based on real measurement. [How] Reduce to the minimum threshold duration, 1us. Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Acked-by:
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Alvin Lee authored
[Description] Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL, OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for more debuggability for a system crash. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
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Leo (Hanghong) Ma authored
[Why && How] OTG can be disabled before setting dpms on. Add check to skip wait when setting AV mute if OTG is disabled. Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
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Alex Hung authored
[WHY] dynamic memory safety error detector (KASAN) catches and generates error messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not support certain features which are not initialized. [HOW] Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3199Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
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Duncan Ma authored
[Why] HPO can be power gated unconditionally for DCN35. [How] Set disable flag to false. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Daniel Miess authored
[Why & How] Enable root clock optimization for HDMISTREAMCLK and only disable it when it's actively being used. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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George Shen authored
[Why/How] Some issues may require a trace of the previous SMU messages from DC to understand the context and aid in debugging. Actual logging to be implemented when needed. Reviewed-by:
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Sung Joon Kim authored
[why] As per programming guide, we need to enable the virtual pixel clock via DTBCLK DTO and ungate the clock before we begin programming OPP/OPTC control registers. Otherwise, the double-buffered registers will be left pending until the clocks are enabled. [how] Move the DTBCLK DTO programming up to where we do the legacy DP DTO programming. Reviewed-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Wenjing Liu authored
[why] There is an ambiguity in subvp pipe topology log. The log doesn't show subvp relation to main stream and it is not clear that certain stream is an internal stream for subvp pipes. [how] Separate subvp pipe topology logging from main pipe topology. Log main stream indices instead of the internal stream for subvp pipes. The following is a sample log showing 2 streams with subvp enabled on both: pipe topology update ________________________ | plane0 slice0 stream0| |DPP1----OPP1----OTG1----| | plane0 slice0 stream1| |DPP0----OPP0----OTG0----| | (phantom pipes) | | plane0 slice0 stream0| |DPP3----OPP3----OTG3----| | plane0 slice0 stream1| |DPP2----OPP2----OTG2----| |________________________| Reviewed-by:
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Dillon Varone authored
[WHY&HOW] Update dmub and driver interface for future FAMS revisions. Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Danijel Slivka authored
Apply this rule to all newer asics in sriov case. For asic with VF MMIO access protection avoid using CPU for VM table updates. CPU pagetable updates have issues with HDP flush as VF MMIO access protection blocks write to BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL register during sriov runtime. Moved the check to amdgpu_device_init() to ensure it is done after amdgpu_device_ip_early_init() where the IP versions are discovered. Signed-off-by:
Danijel Slivka <danijel.slivka@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Arunpravin Paneer Selvam authored
Enable pipe1 support starting from SIENNA CICHLID asic Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2117Reviewed-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
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