1. 18 Apr, 2018 2 commits
    • Matt Redfearn's avatar
      MIPS: uaccess: Add micromips clobbers to bzero invocation · b3d7e55c
      Matt Redfearn authored
      The micromips implementation of bzero additionally clobbers registers t7
      & t8. Specify this in the clobbers list when invoking bzero.
      
      Fixes: 26c5e07d ("MIPS: microMIPS: Optimise 'memset' core library function.")
      Reported-by: default avatarJames Hogan <jhogan@kernel.org>
      Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org> # 3.10+
      Patchwork: https://patchwork.linux-mips.org/patch/19110/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      b3d7e55c
    • Matt Redfearn's avatar
      MIPS: memset.S: Fix clobber of v1 in last_fixup · c96eebf0
      Matt Redfearn authored
      The label .Llast_fixup\@ is jumped to on page fault within the final
      byte set loop of memset (on < MIPSR6 architectures). For some reason, in
      this fault handler, the v1 register is randomly set to a2 & STORMASK.
      This clobbers v1 for the calling function. This can be observed with the
      following test code:
      
      static int __init __attribute__((optimize("O0"))) test_clear_user(void)
      {
        register int t asm("v1");
        char *test;
        int j, k;
      
        pr_info("\n\n\nTesting clear_user\n");
        test = vmalloc(PAGE_SIZE);
      
        for (j = 256; j < 512; j++) {
          t = 0xa5a5a5a5;
          if ((k = clear_user(test + PAGE_SIZE - 256, j)) != j - 256) {
              pr_err("clear_user (%px %d) returned %d\n", test + PAGE_SIZE - 256, j, k);
          }
          if (t != 0xa5a5a5a5) {
             pr_err("v1 was clobbered to 0x%x!\n", t);
          }
        }
      
        return 0;
      }
      late_initcall(test_clear_user);
      
      Which demonstrates that v1 is indeed clobbered (MIPS64):
      
      Testing clear_user
      v1 was clobbered to 0x1!
      v1 was clobbered to 0x2!
      v1 was clobbered to 0x3!
      v1 was clobbered to 0x4!
      v1 was clobbered to 0x5!
      v1 was clobbered to 0x6!
      v1 was clobbered to 0x7!
      
      Since the number of bytes that could not be set is already contained in
      a2, the andi placing a value in v1 is not necessary and actively
      harmful in clobbering v1.
      Reported-by: default avatarJames Hogan <jhogan@kernel.org>
      Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/19109/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      c96eebf0
  2. 17 Apr, 2018 1 commit
    • Matt Redfearn's avatar
      MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup · daf70d89
      Matt Redfearn authored
      The __clear_user function is defined to return the number of bytes that
      could not be cleared. From the underlying memset / bzero implementation
      this means setting register a2 to that number on return. Currently if a
      page fault is triggered within the memset_partial block, the value
      loaded into a2 on return is meaningless.
      
      The label .Lpartial_fixup\@ is jumped to on page fault. In order to work
      out how many bytes failed to copy, the exception handler should find how
      many bytes left in the partial block (andi a2, STORMASK), add that to
      the partial block end address (a2), and subtract the faulting address to
      get the remainder. Currently it incorrectly subtracts the partial block
      start address (t1), which has additionally been clobbered to generate a
      jump target in memset_partial. Fix this by adding the block end address
      instead.
      
      This issue was found with the following test code:
            int j, k;
            for (j = 0; j < 512; j++) {
              if ((k = clear_user(NULL, j)) != j) {
                 pr_err("clear_user (NULL %d) returned %d\n", j, k);
              }
            }
      Which now passes on Creator Ci40 (MIPS32) and Cavium Octeon II (MIPS64).
      Suggested-by: default avatarJames Hogan <jhogan@kernel.org>
      Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/19108/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      daf70d89
  3. 16 Apr, 2018 2 commits
    • Matt Redfearn's avatar
      MIPS: memset.S: EVA & fault support for small_memset · 8a8158c8
      Matt Redfearn authored
      The MIPS kernel memset / bzero implementation includes a small_memset
      branch which is used when the region to be set is smaller than a long (4
      bytes on 32bit, 8 bytes on 64bit). The current small_memset
      implementation uses a simple store byte loop to write the destination.
      There are 2 issues with this implementation:
      
      1. When EVA mode is active, user and kernel address spaces may overlap.
      Currently the use of the sb instruction means kernel mode addressing is
      always used and an intended write to userspace may actually overwrite
      some critical kernel data.
      
      2. If the write triggers a page fault, for example by calling
      __clear_user(NULL, 2), instead of gracefully handling the fault, an OOPS
      is triggered.
      
      Fix these issues by replacing the sb instruction with the EX() macro,
      which will emit EVA compatible instuctions as required. Additionally
      implement a fault fixup for small_memset which sets a2 to the number of
      bytes that could not be cleared (as defined by __clear_user).
      Reported-by: default avatarChuanhua Lei <chuanhua.lei@intel.com>
      Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/18975/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      8a8158c8
    • Matt Redfearn's avatar
      MIPS: dts: Boston: Fix PCI bus dtc warnings: · 2c2bf522
      Matt Redfearn authored
      dtc recently (v1.4.4-8-g756ffc4f52f6) added PCI bus checks. Fix the
      warnings now emitted:
      
      arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@10000000: missing bus-range for PCI bridge
      arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@12000000: missing bus-range for PCI bridge
      arch/mips/boot/dts/img/boston.dtb: Warning (pci_bridge): /pci@14000000: missing bus-range for PCI bridge
      Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: Rob Herring <robh+dt@kernel.org>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: linux-mips@linux-mips.org
      Cc: devicetree@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/19070/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      2c2bf522
  4. 13 Apr, 2018 1 commit
  5. 12 Apr, 2018 1 commit
  6. 06 Apr, 2018 1 commit
  7. 28 Mar, 2018 2 commits
  8. 22 Mar, 2018 1 commit
    • Maciej W. Rozycki's avatar
      MIPS: Use the entry point from the ELF file header · 27c524d1
      Maciej W. Rozycki authored
      In order to fetch the correct entry point with the ISA bit included, for
      use by non-ELF boot loaders, parse the output of `objdump -f' for the
      start address recorded in the kernel executable itself, rather than
      using `nm' to get the value of the `kernel_entry' symbol.
      
      Sign-extend the address retrieved if 32-bit, so that execution is
      correctly started on 64-bit processors as well.  The tool always prints
      the entry point using either 8 or 16 hexadecimal digits, matching the
      address width (aka class) of the ELF file, even in the presence of
      leading zeros.
      Signed-off-by: default avatarMaciej W. Rozycki <macro@mips.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/18912/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      27c524d1
  9. 21 Mar, 2018 6 commits
  10. 14 Mar, 2018 2 commits
  11. 09 Mar, 2018 7 commits
  12. 06 Mar, 2018 3 commits
  13. 05 Mar, 2018 1 commit
    • James Hogan's avatar
      MIPS: Expand help text to list generic defconfigs · cccd0b9a
      James Hogan authored
      Expand the MIPS Makefile help text to list generic board names, generic
      defconfigs, and legacy defconfigs which have been converted to generic
      and are still usable.
      
      Here's a snippet of the new "make ARCH=mips help" output:
        ...
        If you are targeting a system supported by generic kernels you may
        configure the kernel for a given architecture target like so:
      
        {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">
      
        Where BOARDS is some subset of the following:
          boston
          ni169445
          ranchu
          sead-3
          xilfpga
      
        Specifically the following generic default configurations are
        supported:
      
        32r1_defconfig           - Build generic kernel for MIPS32 r1
        32r1el_defconfig         - Build generic kernel for MIPS32 r1 little endian
        32r2_defconfig           - Build generic kernel for MIPS32 r2
        32r2el_defconfig         - Build generic kernel for MIPS32 r2 little endian
        32r6_defconfig           - Build generic kernel for MIPS32 r6
        32r6el_defconfig         - Build generic kernel for MIPS32 r6 little endian
        64r1_defconfig           - Build generic kernel for MIPS64 r1
        64r1el_defconfig         - Build generic kernel for MIPS64 r1 little endian
        64r2_defconfig           - Build generic kernel for MIPS64 r2
        64r2el_defconfig         - Build generic kernel for MIPS64 r2 little endian
        64r6_defconfig           - Build generic kernel for MIPS64 r6
        64r6el_defconfig         - Build generic kernel for MIPS64 r6 little endian
        micro32r2_defconfig      - Build generic kernel for microMIPS32 r2
        micro32r2el_defconfig    - Build generic kernel for microMIPS32 r2 little endian
      
        The following legacy default configurations have been converted to
        generic and can still be used:
      
        sead3_defconfig          - Build 32r2el_defconfig BOARDS=sead-3
        sead3micro_defconfig     - Build micro32r2el_defconfig BOARDS=sead-3
        xilfpga_defconfig        - Build 32r2el_defconfig BOARDS=xilfpga
        ...
      Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paul Burton <paul.burton@mips.com>
      Cc: Matt Redfearn <matt.redfearn@mips.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kbuild@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/18598/
      cccd0b9a
  14. 19 Feb, 2018 10 commits