Merge tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

soc/tegra: Changes for v5.5-rc1

Adds wake event support on Tegra210, implements the NVMEM API for the
Tegra FUSE block and adds coupled regulators support for Tegra20 and
Tegra30.

* tag 'tegra-for-5.5-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Remove unnecessary memory barrier
  soc/tegra: pmc: Query PCLK clock rate at probe time
  soc/tegra: regulators: Add regulators coupler for Tegra30
  soc/tegra: regulators: Add regulators coupler for Tegra20
  soc/tegra: pmc: Configure deep sleep control settings
  soc/tegra: pmc: Configure core power request polarity
  soc/tegra: pmc: Add wake event support on Tegra210
  soc/tegra: pmc: Support wake events on more Tegra SoCs
  soc/tegra: fuse: Register cell lookups for compatibility
  soc/tegra: fuse: Add cell information
  soc/tegra: fuse: Implement nvmem device
  soc/tegra: fuse: Restore base on sysfs failure
  soc/tegra: pmc: Fix crashes for hierarchical interrupts
  soc/tegra: fuse: Add FUSE clock check in tegra_fuse_readl()

Link: https://lore.kernel.org/r/20191102144521.3863321-4-thierry.reding@gmail.comSigned-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'tegra-for-5.5-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

firmware: tegra: Changes for v5.5-rc1

This contains a single fix for suspend/resume on Tegra194.

* tag 'tegra-for-5.5-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  firmware: tegra: Move BPMP resume to noirq phase

Link: https://lore.kernel.org/r/20191102144521.3863321-2-thierry.reding@gmail.comSigned-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.5 (take two)

  - Initial support for the R-Car M3-W+ (r8a77961) SoC,
  - A minor fix.

* tag 'renesas-drivers-for-v5.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-sysc: Add R8A77961 support
  soc: renesas: rcar-rst: Add R8A77961 support
  soc: renesas: Identify R-Car M3-W+
  soc: renesas: Add ARCH_R8A77961 for new R-Car M3-W+
  soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W
  soc: renesas: Rename SYSC_R8A7796 to SYSC_R8A77960
  soc: renesas: Add missing check for non-zero product register address
  dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions
  dt-bindings: power: Add r8a77961 SYSC power domain definitions

Link: https://lore.kernel.org/r/20191101155842.31467-6-geert+renesas@glider.beSigned-off-by: Olof Johansson <olof@lixom.net>

Merge branch 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers

* 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
  memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs'
  soc: ti: omap-prm: fix return value check in omap_prm_probe()
  soc: ti: omap-prm: add omap5 PRM data
  soc: ti: omap-prm: add am4 PRM data
  soc: ti: omap-prm: add dra7 PRM data
  soc: ti: omap-prm: add data for am33xx
  soc: ti: omap-prm: add omap4 PRM data
  soc: ti: omap-prm: add support for denying idle for reset clockdomain
  soc: ti: omap-prm: poll for reset complete during de-assert
  soc: ti: add initial PRM driver with reset control support
  dt-bindings: omap: add new binding for PRM instances

Link: https://lore.kernel.org/r/1572372856-20598-1-git-send-email-santosh.shilimkar@oracle.comSigned-off-by: Olof Johansson <olof@lixom.net>

Add support for the power areas in the Renesas R-Car M3-W+ (R8A77961)
SoC to the R-Car System Controller driver.

R-Car M3-W+ (aka R-Car M3-W ES3.0) is very similar to R-Car
M3-W (R8A77960), which allows for both SoCs to share a driver:
  - R-Car M3-W+ lacks the A2VC power area, so its area must be
    nullified,
  - The existing support for the SYSCEXTMASK register added in commit
    9bd645af9d2a49ac ("soc: renesas: r8a7796-sysc: Fix power request
    conflicts") applies to ES3.0 and later only.
    As R-Car M3-W+ uses a different compatible value, differentiate
    based on that, instead of on the ES version.

Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-7-geert+renesas@glider.be

Add support for the Reset block in the R-Car M3-W+ (R8A77961) SoC to the
Renesas R-Car RST driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-6-geert+renesas@glider.be

Add support for identifying the R-Car M3-W+ (R8A77961) SoC, which shares
the Product ID Number with R-Car M3-W (R8A77960), but differs in CUT
Number (Ver. 3.0), and uses a different compatible value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-5-geert+renesas@glider.be

Add CONFIG_ARCH_R8A77961 as a configuration symbol for the new Renesas
R-Car M3-W+ (R8A77961) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-4-geert+renesas@glider.be

Add CONFIG_ARCH_R8A77960 as a new config symbol for R-Car M3-W
(R8A77960), to replace CONFIG_ARCH_R8A7796, and avoid confusion with
R-Car M3-W+ (R8A77961), which will use CONFIG_ARCH_R8A77961.

Note that for now, CONFIG_ARCH_R8A7796 is retained, and just selects
CONFIG_ARCH_R8A77960.  This relaxes dependencies of other subsystems on
the SoC configuration symbol, and provides a smooth transition path for
config files through "make oldconfig".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-3-geert+renesas@glider.be

Rename CONFIG_SYSC_R8A7796 for R-Car M3-W (R8A77960) to
CONFIG_SYSC_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961),
which will use CONFIG_SYSC_R8A77961.

Rename r8a7796_sysc_info and r8a7796_sysc_init for consistency.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191023123342.13100-2-geert+renesas@glider.be

Renesas R-Car M3-W+ DT Binding Definitions

Clock and Power Domain definitions for the Renesas R-Car M3-W+
(R8A77961) SoC, shared by driver and DT source files.

If the DTB for a device with an RZ/A2 SoC lacks a device node for the
BSID register, the ID validation code falls back to using a register at
address 0x0, which leads to undefined behavior (e.g. reading back a
random value).

This could be fixed by letting fam_rza2.reg point to the actual BSID
register.  However, the hardcoded fallbacks were meant for backwards
compatibility with old DTBs only, not for new SoCs.  Hence fix this by
validating renesas_family.reg before using it.

Fixes: 175f435f ("soc: renesas: identify RZ/A2")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191016143306.28995-1-geert+renesas@glider.be

Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
M3-W+ (R8A77961) SoC, as listed in Table 8.2b ("List of Clocks [R-Car
M3-W/R-Car M3-W+]") of the R-Car Series, 3rd Generation Hardware User's
Manual (Rev. 2.00, Jul. 31, 2019).  A gap is added for CSIREF, to
preserve compatibility with the definitions for R-Car M3-W (R8A77960).

Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, SSPSRC, and POST2)
are not included, as they are used as internal clock sources only, and
never referenced from DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20191023122941.12342-3-geert+renesas@glider.be

Add power domain indices for the R-Car M3-W+ (R8A77961) SoC.

Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s
Manual (Jul. 31, 2019).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191023122911.12166-6-geert+renesas@glider.be

drivers/memory/emif.c:1616:9: warning:
 variable cs1_used set but not used [-Wunused-but-set-variable]
drivers/memory/emif.c:1624:36: warning:
 variable custom_configs set but not used [-Wunused-but-set-variable]

They are never used since introduction.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>

In case of error, the function devm_ioremap_resource() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().

Fixes: 3e99cb21 ("soc: ti: add initial PRM driver with reset control support")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>

The removed barrier isn't needed because writes/reads are strictly ordered
and even if PMC had separate ports for writes, it wouldn't matter since
the hardware logic takes into effect after triggering CPU's power-gating
and at that point all CPU accesses are guaranteed to be completed. That
barrier was copied from the old arch/ code during transition to the soc/
PMC driver and even that the code structure was different back then, the
barrier didn't have a real useful purpose from the start. Lastly, the
tegra_pmc_writel() naturally inserts wmb() because it uses writel(),
and thus this change doesn't actually make any difference in terms of
interacting with hardware. Hence let's remove the barrier to clean up
code a tad.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

It is possible to get a lockup if kernel decides to enter LP2 cpuidle
from some clk-notifier, in that case CCF's "prepare" mutex is kept locked
and thus clk_get_rate(pclk) blocks on the same mutex with interrupts being
disabled, hanging machine.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add regulators coupler for Tegra30 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 2 coupled regulators on all Tegra30 SoCs: CORE and CPU. The
coupled regulator voltages shall be in a range of 300mV from each other
and CORE voltage shall be higher than the CPU by N mV, where N depends
on the CPU voltage.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add regulators coupler for Tegra20 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.

There are 3 coupled regulators on all Tegra20 SoCs: CORE, RTC and CPU.
The CORE and RTC voltages shall be in range of 170mV from each other and
they both shall be higher than the CPU voltage by at least 120mV. This
sounds like it could be handle by a generic voltage balancer, but the CORE
voltage scaling isn't implemented in any of the upstream drivers yet.
It will take quite some time and effort to hook up voltage scaling for
all of the drivers, hence we will use a custom coupler that will manage
the CPU voltage scaling for the starter.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra210 and prior Tegra chips have deep sleep entry and wakeup related
timings which are platform specific that should be configured before
entering into deep sleep.

Below are the timing specific configurations for deep sleep entry and
wakeup.
- Core rail power-on stabilization timer
- OSC clock stabilization timer after SOC rail power is stabilized.
- Core power off time is the minimum wake delay to keep the system
  in deep sleep state irrespective of any quick wake event.

These values depends on the discharge time of regulators and turn OFF
time of the PMIC to allow the complete system to finish entering into
deep sleep state.

These values vary based on the platform design and are specified
through the device tree.

This patch has implementation to configure these timings which are must
to have for proper deep sleep and wakeup operations.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

This patch configures polarity of the core power request signal
in PMC control register based on the device tree property.

PMC asserts and de-asserts power request signal based on it polarity
when it need to power-up and power-down the core rail during SC7.
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

This patch implements PMC wakeup sequence for Tegra210 and defines the
commonly used RTC alarm wake event.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

This patch allows to create separate irq_set_wake and irq_set_type
implementations for different Tegra designs PMC that has different
wake models which require difference wake registers and different
programming sequence.

AOWAKE model support is available for Tegra186 and Tegra194 only
and it resides within PMC and supports tiered wake architecture.

Tegra210 and prior Tegra designs uses PMC directly to receive wake
events and coordinate the wake sequence.
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Reset controller updates for v5.5

This tag adds support for Meson SM1 ARB resets, Uniphier Pro5 USB3
resets, the Meson-A1 reset controller, SocFPGA Agilex resets, and
Realtek RTD1195/RTD1295 resets.
It adds some reset controller API keywords for get_maintainers.pl and
makes a few remaining reset_control_ops const. Also included are
a conversion of the Qualcomm device tree bindings to yaml and a few
small kerneldoc improvements.

* tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux:
  reset: document (devm_)reset_control_get_optional variants
  reset: improve of_xlate documentation
  reset: simple: Add Realtek RTD1195/RTD1295
  reset: simple: Keep alphabetical order
  MAINTAINERS: add reset controller framework keywords
  reset: zynqmp: Make reset_control_ops const
  reset: hisilicon: hi3660: Make reset_control_ops const
  reset: build simple reset controller driver for Agilex
  reset: add support for the Meson-A1 SoC Reset Controller
  dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
  reset: uniphier-glue: Add Pro5 USB3 support
  dt-bindings: reset: pdc: Convert PDC Global bindings to yaml
  dt-bindings: reset: aoss: Convert AOSS reset bindings to yaml
  reset: Remove copy'n'paste redundancy in the comments
  reset: meson-audio-arb: add sm1 support
  reset: dt-bindings: meson: update arb bindings for sm1

Link: https://lore.kernel.org/r/ede6874508472d0917dca770ef80b90626b0f205.camel@pengutronix.deSigned-off-by: Olof Johansson <olof@lixom.net>

Add kerneldoc comments for the optional reset_control_get variants.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Mention of_reset_simple_xlate as the default if of_xlate is not set.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Enable RESET_SIMPLE for ARCH_REALTEK.
They can reuse the DesignWare bindings to avoid a new compatible.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Restore alphabetical order for Kconfig dependencies and help text.
Compatibles got out of order too, but no functional change done here.

Goal is to make it obvious where to add new platforms.

Fixes: 64c47b62 ("reset: Add reset controller support for BM1880 SoC")
Fixes: 1d7592f8 ("reset: simple: Enable for ASPEED systems")
Fixes: 96a2f503 ("reset: build simple reset controller driver for Agilex")
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

This pull request contains Broadcom ARM/ARM64/MIPS based SoCs drivers
updates for 5.5, please pull the following:

- Markus updates the DPFE driver so as to support deferring the firmware
  loading process until the first sysfs attribute is accessed, in the
  process he does a bunch of cleanups and minor fixes

- Florian adds support for the DPFE on 7211 which uses a "new style" API
  v2 and makes necessary changes along the way

* tag 'arm-soc/for-5.5/drivers' of https://github.com/Broadcom/stblinux:
  memory: brcmstb: dpfe: Fixup API version/commands for 7211
  memory: brcmstb: dpfe: Compute checksum at __send_command() time
  memory: brcmstb: dpfe: support for deferred firmware download
  memory: brcmstb: dpfe: pass *priv as argument to brcmstb_dpfe_download_firmware()
  memory: brcmstb: dpfe: move init_data into brcmstb_dpfe_download_firmware()
  memory: brcmstb: dpfe: add locking around DCPU enable/disable
  memory: brcmstb: dpfe: initialize priv->dev
  memory: brcmstb: dpfe: rename struct private_data

Link: https://lore.kernel.org/r/20191023212814.30622-2-f.fainelli@gmail.comSigned-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'omap-for-v5.5/ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/drivers

Changes for ti-sysc interconnect target module driver for v5.5

A series of changes from Tero Kristo for rpm reset control
driver to deal with the ordering requirements between clocks
and resets, and two changes to deal with quirks for musb otg
device.

* tag 'omap-for-v5.5/ti-sysc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  bus: ti-sysc: Use swsup quirks also for am335x musb
  bus: ti-sysc: Handle mstandby quirk and use it for musb
  bus: ti-sysc: Fix watchdog quirk handling
  bus: ti-sysc: avoid toggling power state of module during probe
  bus: ti-sysc: drop the extra hardreset during init
  bus: ti-sysc: re-order reset and main clock controls

Link: https://lore.kernel.org/r/pull-1571853258-16998@atomide.com-2Signed-off-by: Olof Johansson <olof@lixom.net>

Add a regex that matches users of the reset controller API.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The zynqmp_reset_ops structure is never modified. Make it const.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The hi3660_reset_ops structure is never modified. Make it const.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

The Intel SoCFPGA Agilex platform shares the same reset controller that
is on the Stratix10.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Since this driver is enabled for COMPILE_TEST, it avoids build error
on x86 allmodconfig:

In file included from /build/drivers/phy/marvell/phy-mmp3-usb.c:12:
/build/include/linux/soc/mmp/cputype.h:5:10: fatal error: asm/cputype.h: No such file or directory

Link: https://lore.kernel.org/r/20191022015658.14624-1-olof@lixom.netSigned-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'mmp-drivers-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp into arm/drivers

ARM: Marvell MMP driver patches for v5.5

This tag includes the MMP3 USB2 PHY driver. The branch is based on
mmp-soc-for-v5.5-2 because the driver depends on changes in MMP SoC
support.

* tag 'mmp-drivers-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp:
  MAINTAINERS: phy: add entry for USB PHY drivers on MMP SoCs
  phy: Add USB2 PHY driver for Marvell MMP3 SoC
  MAINTAINERS: mmp: add Git repository
  ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h
  ARM: mmp: move cputype.h to include/linux/soc/
  ARM: mmp: add SMP support
  ARM: mmp: add support for MMP3 SoC
  ARM: mmp: define MMP_CHIPID by the means of CIU_REG()
  ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE
  ARM: mmp: map the PGU as well
  ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP
  ARM: l2c: add definition for FWA in PL310 aux register

Link: https://lore.kernel.org/r/7cee3ddbb553ba7fe6e1420e0dbc5adb4922b317.camel@v3.skSigned-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'samsung-drivers-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers

Samsung DMC driver for v5.5

Add Samsung Dynamic Memory Controller for Exynos5422 which provides
scaling of frequency and voltage of memory controller and DRAM.  The
driver allows to reduce energy usage without performance impact.

* tag 'samsung-drivers-dmc-5.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  memory: samsung: exynos5422-dmc: Add support for interrupt from performance counters
  memory: samsung: exynos5422-dmc: Fix kfree() of devm-allocated memory and missing static
  memory: samsung: exynos5422-dmc: Fix spelling mistake "counld" -> "could"
  memory: Add DMC driver for Exynos5422
  memory: Extend of_memory with LPDDR3 support

Link: https://lore.kernel.org/r/20191021180453.29455-3-krzk@kernel.orgSigned-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-drivers-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers

Renesas driver updates for v5.5

  - Add support for the new RZ/G2N (r8a774b1) SoC,
  - Fix System Controller power request conflicts on recent R-Car Gen3
    and RZ/G2N SoC variants and revisions,
  - Minor cleanups.

* tag 'renesas-drivers-for-v5.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-sysc: Add r8a774b1 support
  soc: renesas: rcar-sysc: Remove unneeded inclusion of <linux/bug.h>
  soc: renesas: r8a774c0-sysc: Fix power request conflicts
  soc: renesas: rcar-rst: Add support for RZ/G2N
  soc: renesas: Identify RZ/G2N
  soc: renesas: Add Renesas R8A774B1 config option
  soc: renesas: r8a77990-sysc: Fix power request conflicts
  soc: renesas: r8a77980-sysc: Fix power request conflicts
  soc: renesas: r8a77970-sysc: Fix power request conflicts
  soc: renesas: r8a77965-sysc: Fix power request conflicts
  soc: renesas: r8a7796-sysc: Fix power request conflicts
  soc: renesas: r8a7795-sysc: Fix power request conflicts
  soc: renesas: rcar-sysc: Prepare for fixing power request conflicts
  dt-bindings: clk: Add r8a774b1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774b1 SYSC power domain definitions

Link: https://lore.kernel.org/r/20191018101136.26350-5-geert+renesas@glider.beSigned-off-by: Olof Johansson <olof@lixom.net>

Also on am335x we need the swsup quirks for musb.
Signed-off-by: Tony Lindgren <tony@atomide.com>