- 15 Apr, 2022 34 commits
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Tianjia Zhang authored
Commit d2825fa9 ("crypto: sm3,sm4 - move into crypto directory") moved the sm4 library implementation from the lib/crypto directory to the crypto directory and configured the name as CRYPTO_SM4. The arm64 SM4 NEON/CE implementation depends on this and needs to be modified uniformly. Fixes: 4f1aef9b ("crypto: arm64/sm4 - add ARMv8 NEON implementation") Fixes: 5b33e0ec ("crypto: arm64/sm4 - add ARMv8 Crypto Extensions implementation") Signed-off-by:
Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Yang Shen authored
The hardware needs aligned sgl dma address. So expend the sgl_size to align 64 bytes. Signed-off-by:
Yang Shen <shenyang39@huawei.com> Signed-off-by:
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Kai Ye authored
1. Add some debugging registers. 2. Add last word dumping function during zip engine controller reset. Signed-off-by:
Kai Ye <yekai13@huawei.com> Signed-off-by:
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Kai Ye authored
1. Add some debugging registers. 2. Add last word dumping function during hpre engine controller reset. Signed-off-by:
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Kai Ye authored
Add last word dumping function during sec engine controller reset. Signed-off-by:
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Kai Ye authored
Add last word dumping function during acc engines controller reset. The last words are reported to the printed information during the reset. The dmesg information included qm debugging registers and engine debugging registers. It can help to improve debugging capability. Signed-off-by:
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Kai Ye authored
Update documentation describing DebugFS that could help to check the change of register values. Signed-off-by:
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Kai Ye authored
Update documentation describing DebugFS that could help to check the change of register values. Signed-off-by:
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Kai Ye authored
Update documentation describing DebugFS that could help to check the change of register values. Signed-off-by:
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Kai Ye authored
The value of the register is changed after the task running. A debugfs file node is added to help users to check the change of register values. Signed-off-by:
Longfang Liu <liulongfang@huawei.com> Signed-off-by:
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Kai Ye authored
The value of the register is changed after the task running. A debugfs file node is added to help users to check the change of register values. Signed-off-by:
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Kai Ye authored
The value of the register is changed after the task running. A debugfs file node is added to help users to check the change of register values. Signed-off-by:
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Kai Ye authored
Add register detection function to accelerator. Provided a tool that user can checking differential register through Debugfs. e.g. cd /sys/kernel/debug/hisi_zip/<bdf>/zip_dfx cat diff_regs Signed-off-by: -
Yihao Han authored
Replace `if (!req_ctx->updated)` with `else` for simplification and add curly brackets according to the kernel coding style: "Do not unnecessarily use braces where a single statement will do." ... "This does not apply if only one branch of a conditional statement is a single statement; in the latter case use braces in both branches" Please refer to: https://www.kernel.org/doc/html/v5.17-rc8/process/coding-style.htmlSigned-off-by:
Yihao Han <hanyihao@vivo.com> Signed-off-by:
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Conor Dooley authored
Add a driver to access the hardware random number generator on the Polarfire SoC. The hwrng can only be accessed via the system controller, so use the mailbox interface the system controller exposes to access the hwrng. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Marco Chiappero authored
Remove unnecessary line wrapping for the adf_enable_vf2pf_interrupts() function, and harmonize pfvf_ops text. Signed-off-by:
Marco Chiappero <marco.chiappero@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
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Marco Chiappero authored
Change adf_gen4_enable_vf2pf_interrupts() to use a u32 variable, consistently with both other GEN4 pfvf_ops and pfvf_ops of other generations. Signed-off-by:
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Marco Chiappero authored
As a consequence of the refactored VF2PF interrupt handling logic, a function that disables specific VF2PF interrupts is no longer needed. Instead, a simpler function that disables all the interrupts, also hiding the device specific amount of VFs to be disabled from the pfvf_ops users, would be sufficient. This patch replaces disable_vf2pf_interrupts() with the new disable_all_vf2pf_interrupts(), which doesn't need any argument and disables all the VF2PF interrupts. Signed-off-by:
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Marco Chiappero authored
Replace hard coded VF masks in adf_gen2_pfvf.c with the recently introduced ADF_GEN2_VF_MSK. Signed-off-by:
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Marco Chiappero authored
Change the VF2PF interrupt handler in the PF ISR and the definition of the internal PFVF API to correct the current implementation, which can result in missed interrupts. More specifically, current HW generations consider a write to the mask register, regardless of the value, as an acknowledge of any pending VF2PF interrupt. Therefore, if there is an interrupt between the source register read and the mask register write, such interrupt will not be delivered and silently acknowledged, resulting in a lost VF2PF message. To work around the problem, rather than disabling specific interrupts, disable all the interrupts and re-enable only the ones that we are not serving (excluding the already disabled ones too). This will force any other pending interrupt to be triggered and be serviced by a subsequent ISR. This new approach requires, however, changes to the interrupt related pfvf_ops functions. In particular, get_vf2pf_sources() has now been removed in favor of disable_pending_vf2pf_interrupts(), which not only retrieves and returns the pending (and enabled) sources, but also disables them. As a consequence, introduce the adf_disable_pending_vf2pf_interrupts() utility in place of adf_disable_vf2pf_interrupts_irq(), which is no longer needed. Cc: stable@vger.kernel.org Fixes: 993161d3 ("crypto: qat - fix handling of VF to PF interrupts") Signed-off-by:
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Marco Chiappero authored
PFVF Block Message requests for CRC use 0-based values to indicate amounts, which have to be remapped to 1-based values on the receiving side. This patch fixes one debug print which was however using the wire value. Signed-off-by:
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Marco Chiappero authored
Remove an unintentional extra space and improve the readability of a PFVF related code comment. Signed-off-by:
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Marco Chiappero authored
Spurious PFVF interrupts can happen when either the ISR is invoked without a valid source being set or, otherwise, when no interrupt bit is set in the PFVF register containing the message. The latter test was present for GEN2 devices but missing for GEN4, this patch fills the gap. Signed-off-by:
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Wojciech Ziemba authored
PFVF protocol version 0 is not a valid version, but PF drivers currently would report any such version from VFs as compatible. This patch adds an extra check for the invalid PFVF protocol version 0. Signed-off-by:
Wojciech Ziemba <wojciech.ziemba@intel.com> Signed-off-by:
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Marco Chiappero authored
VF drivers are notified via PFVF of the VFs being disabled, but such notification was not propagated within the VF driver. Dispatch the ADF_EVENT_RESTARTING event by adding a missing call to adf_dev_restarting_notify(). Signed-off-by:
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Marco Chiappero authored
Previously, the GEN4 host driver supported SR-IOV but had no working implementation of the PFVF protocol to communicate with VF drivers. Since all the host drivers for QAT devices now support both SR-IOV and PFVF, remove the old and unnecessary checks to test PFVF support. Signed-off-by:
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Giovanni Cabiddu authored
The functions adf_enable_pf2vf_interrupts(), adf_flush_vf_wq() and adf_disable_pf2vf_interrupts() are not referenced when the driver is compiled with CONFIG_PCI_IOV=n. This patch removes these unused stubs. Signed-off-by:
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Marco Chiappero authored
Remove unnecessary braces around a single statement in a for loop. Signed-off-by:
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Marco Chiappero authored
When the driver starts the device, it enables all the necessary interrupts. However interrupts associated to host rings are enabled by default on all GEN2 devices (except for dh895x) even when SR-IOV is active. Fix this behaviour by checking if data structures associated to VFs have been allocated to determine whether to enable such interrupts or not. Since the logic for the fix is the same across GEN2 devices, replace the function to be fixed (adf_enable_ints()) with a single one (adf_gen2_enable_ints()) in the common GEN2 code in adf_gen2_hw_data.c. Likewise, remove the unnecessary duplication of defines too. Signed-off-by:
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Giovanni Cabiddu authored
The capability detection logic clears bits for the features that are disabled in a certain SKU. For example, if the bit associate to compression is not present in the LEGFUSE register, the correspondent bit is cleared in the capability mask. This change adds the compression capability to the mask as this was missing in the commit that enhanced the capability detection logic. Fixes: cfe4894e ("crypto: qat - set COMPRESSION capability for QAT GEN2") Signed-off-by:
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Giovanni Cabiddu authored
Set the CIPHER capability for QAT DH895XCC devices if the hardware supports it. This is done if both the CIPHER and the AUTHENTICATION engines are available on the device. Fixes: ad1332aa ("crypto: qat - add support for capability detection") Signed-off-by:
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Gilad Ben-Yossef authored
Use a fine grained specification of DMA mapping directions in certain cases, allowing both a more optimized operation as well as shushing out a harmless, though persky dma-debug warning. Signed-off-by:
Gilad Ben-Yossef <gilad@benyossef.com> Reported-by:
Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by:
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Gilad Ben-Yossef authored
Rearrange init calls to avoid the rare race condition of the cipher algs being registered and used while we still init the hash code which uses the HW without proper lock. Signed-off-by:
Dung Nguyen <dung.nguyen.zy@renesas.com> Tested-by:
Jing Dan <jing.dan.nx@renesas.com> Tested-by:
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Robin Murphy authored
Even if an IOMMU might be present for some PCI segment in the system, that doesn't necessarily mean it provides translation for the device we care about. Replace iommu_present() with a more appropriate check. Signed-off-by:
Robin Murphy <robin.murphy@arm.com> Acked-by:
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- 08 Apr, 2022 6 commits
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Jakob Koschel authored
When list_for_each_entry() completes the iteration over the whole list without breaking the loop, the iterator value will be a bogus pointer computed based on the head element. While it is safe to use the pointer to determine if it was computed based on the head element, either with list_entry_is_head() or &pos->member == head, using the iterator variable after the loop should be avoided. In preparation to limit the scope of a list iterator to the list traversal loop, use a dedicated pointer to point to the found element [1]. Link: https://lore.kernel.org/all/CAHk-=wgRr_D8CB-D9Kg-c=EHreAsk5SqXPwr9Y7k9sA6cWXJ6w@mail.gmail.com/ [1] Signed-off-by:
Jakob Koschel <jakobkoschel@gmail.com> Signed-off-by:
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Mario Limonciello authored
CC_ATTR_HOST_MEM_ENCRYPT is used to relay that memory encryption has been activated by the kernel. As it's technically possible to enable both SME and TSME at the same time, detect this scenario and notify the user that enabling TSME and SME at the same time is unnecessary. Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by:
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Mario Limonciello authored
Previously the PSP probe routine would fail if both SEV and TEE were missing. This is possibly the case for some client parts. As capabilities can now be accessed from userspace, it may still be useful to have the PSP driver finish loading so that those capabilities can be read. Signed-off-by:
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Mario Limonciello authored
The PSP sets several pre-defined bits in the capabilities register to indicate that security attributes of the platform. Export these attributes into userspace for administrators to confirm platform is properly locked down. Acked-by:
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Mario Limonciello authored
The results of the capability register will be used by future code at runtime rather than just initialization. Acked-by:
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Eric Biggers authored
As was established in the thread https://lore.kernel.org/linux-crypto/20220223080400.139367-1-gilad@benyossef.com/T/#u, many crypto API users doing in-place en/decryption don't use the same scatterlist pointers for the source and destination, but rather use separate scatterlists that point to the same memory. This case isn't tested by the self-tests, resulting in bugs. This is the natural usage of the crypto API in some cases, so requiring API users to avoid this usage is not reasonable. Therefore, update the self-tests to start testing this case. Signed-off-by:
Eric Biggers <ebiggers@google.com> Signed-off-by:
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