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  1. 23 Nov, 2018 1 commit
  3. 02 Oct, 2018 1 commit
  5. 29 Aug, 2018 3 commits
  7. 06 Aug, 2018 1 commit
    • Quentin Schulz's avatar
      pinctrl: ocelot: add support for interrupt controller · be36abb7
      Quentin Schulz authored 
      This GPIO controller can serve as an interrupt controller as well on the
GPIOs it handles.

An interrupt is generated whenever a GPIO line changes and the
interrupt for this GPIO line is enabled. This means that both the
changes from low to high and high to low generate an interrupt.

For some use cases, it makes sense to ignore the high to low change and
not generate an interrupt. Such a use case is a line that is hold in a
level high/low manner until the event holding the line gets acked.
This can be achieved by making sure the interrupt on the GPIO controller
side gets acked and masked only after the line gets hold in its default
state, this is what's done with the fasteoi functions.

Only IRQ_TYPE_EDGE_BOTH and IRQ_TYPE_LEVEL_HIGH are supported for now.
Signed-off-by: default avatarQuentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      be36abb7
  9. 18 Jun, 2018 1 commit
  11. 05 Jun, 2018 1 commit
    • Richard Fitzgerald's avatar
      pinctrl: madera: Add driver for Cirrus Logic Madera codecs · 218d72a7
      Richard Fitzgerald authored 
      These codecs have a variable number of I/O lines each of which
is individually selectable to a wide range of possible functions.

The functionality is slightly different from the traditional muxed
GPIO since most of the functions can be mapped to any pin (and even
the same function to multiple pins). Most pins have a dedicated
"alternate" function that is only available on that pin. The
alternate functions are usually a group of signals, though it is
not always necessary to enable the full group, depending on the
alternate function and how it is to be used. The mapping between
alternate functions and GPIO pins varies between codecs depending
on the number of alternate functions and available pins.
Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarLee Jones <lee.jones@linaro.org>
      218d72a7
  13. 02 May, 2018 1 commit
  15. 26 Mar, 2018 1 commit
  17. 01 Mar, 2018 1 commit
  19. 09 Jan, 2018 1 commit
  21. 20 Dec, 2017 1 commit
  23. 07 Dec, 2017 1 commit
  25. 13 Nov, 2017 1 commit
  27. 08 Nov, 2017 1 commit
  29. 19 Oct, 2017 1 commit
    • Linus Walleij's avatar
      pinctrl: adi2: Fix Kconfig build problem · 1c363531
      Linus Walleij authored 
      The build robot is complaining on Blackfin:

drivers/pinctrl/pinctrl-adi2.c: In function 'port_setup':
>> drivers/pinctrl/pinctrl-adi2.c:221:21: error: dereferencing
   pointer to incomplete type 'struct gpio_port_t'
      writew(readw(&regs->port_fer) & ~BIT(offset),
                        ^~
drivers/pinctrl/pinctrl-adi2.c: In function 'adi_gpio_ack_irq':
>> drivers/pinctrl/pinctrl-adi2.c:266:18: error: dereferencing
pointer to incomplete type 'struct bfin_pint_regs'
      if (readl(&regs->invert_set) & pintbit)
                     ^~
It seems the driver need to include <asm/gpio.h> and <asm/irq.h>
to compile.

The Blackfin architecture was re-defining the Kconfig
PINCTRL symbol which is not OK, so replaced this with
PINCTRL_BLACKFIN_ADI2 which selects PINCTRL and PINCTRL_ADI2
just like most arches do.

Further, the old GPIO driver symbol GPIO_ADI was possible to
select at the same time as selecting PINCTRL. This was not
working because the arch-local <asm/gpio.h> header contains
an explicit #ifndef PINCTRL clause making compilation break
if you combine them. The same is true for DEBUG_MMRS.

Make sure the ADI2 pinctrl driver is not selected at the same
time as the old GPIO implementation. (This should be converted
to use gpiolib or pincontrol and move to drivers/...) Also make
sure the old GPIO_ADI driver or DEBUG_MMRS is not selected at
the same time as the new PINCTRL implementation, and only make
PINCTRL_ADI2 selectable for the Blackfin families that actually
have it.

This way it is still possible to add e.g. I2C-based pin
control expanders on the Blackfin.

Cc: Steven Miao <realmz6@gmail.com>
Cc: Huanhuan Feng <huanhuan.feng@analog.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      1c363531
  31. 16 Oct, 2017 1 commit
  33. 12 Oct, 2017 1 commit
  35. 11 Oct, 2017 1 commit
  37. 27 Sep, 2017 1 commit
    • Petr Mladek's avatar
      pinctrl/amd: Fix build dependency on pinmux code · 83b31c2a
      Petr Mladek authored 
      The commit 79d2c8be ("pinctrl/amd: save pin registers over
suspend/resume") caused the following compilation errors:

drivers/pinctrl/pinctrl-amd.c: In function ‘amd_gpio_should_save’:
drivers/pinctrl/pinctrl-amd.c:741:8: error: ‘const struct pin_desc’ has no member named ‘mux_owner’
  if (pd->mux_owner || pd->gpio_owner ||
        ^
drivers/pinctrl/pinctrl-amd.c:741:25: error: ‘const struct pin_desc’ has no member named ‘gpio_owner’
  if (pd->mux_owner || pd->gpio_owner ||

We need to enable CONFIG_PINMUX for this driver as well.

Cc: stable@vger.kernel.org
Fixes: 79d2c8be ("pinctrl/amd: save pin registers over suspend/resume")
Signed-off-by: default avatarPetr Mladek <pmladek@suse.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      83b31c2a
  39. 31 Aug, 2017 1 commit
  41. 21 Aug, 2017 1 commit
  43. 14 Aug, 2017 1 commit
  45. 23 Jun, 2017 1 commit
  47. 30 May, 2017 1 commit
    • Arnd Bergmann's avatar
      pinctrl: mcp23s08: improve I2C Kconfig dependency · adeac775
      Arnd Bergmann authored 
      With "SPI_MASTER=y && I2C=m", we can build mcp23s08 as a built-in driver,
which then results in a link failure:

drivers/pinctrl/built-in.o: In function `mcp23s08_probe_one.isra.0':
:(.text+0x7910): undefined reference to `__devm_regmap_init_i2c'
drivers/pinctrl/built-in.o: In function `mcp23s08_init':
:(.init.text+0x110): undefined reference to `i2c_register_driver'
drivers/pinctrl/built-in.o: In function `mcp23s08_exit':
:(.exit.text+0x3c): undefined reference to `i2c_del_driver'

To avoid the problem, this adds another dependency on I2C that enforces
mcp23s08 to be a loadable module whenever the I2C core is a module.

Fixes: 64ac43e6 ("gpio: mcp23s08: move to pinctrl")
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      adeac775
  49. 29 May, 2017 1 commit
  51. 23 May, 2017 3 commits
  53. 22 May, 2017 2 commits
    • Paul Cercueil's avatar
      pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs · b5c23aa4
      Paul Cercueil authored 
      This driver handles pin configuration and pin muxing for the
JZ4740 and JZ4780 SoCs from Ingenic.
Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      b5c23aa4
    • Shawn Guo's avatar
      pinctrl: add ZTE ZX pinctrl driver support · cbff0c4d
      Shawn Guo authored 
      The pin controller on ZTE ZX platforms is kinda of hybrid.  It consists
of a main controller and an auxiliary one.  For example, on ZX296718 SoC,
the main controller is TOP_PMM and the auxiliary one is AON_IOCFG.  Both
controllers work together to control pin multiplexing and configuration.

For most of pins, the pinmux function is controlled by main controller
only, and this type of pins are meant by term 'TOP pins'.  For other
pins, the pinmux is controlled by both main and auxiliary controllers,
as the available multiplexing functions for the pin spread in both
controllers.  This type of pins are called 'AON pins'.  Though pinmux
implementation is quite different, pinconf is same for both types of
pins.  Both are controlled by auxiliary controller, i.e. AON_IOCFG on
ZX296718.

The patch adds the ZTE ZX core pinctrl driver to support this hybrid
pin controller as well as ZX296718 SoC specific pin data.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      cbff0c4d
  55. 07 Apr, 2017 1 commit
  57. 09 Jan, 2017 1 commit
    • Nishanth Menon's avatar
      pinctrl: Introduce TI IOdelay configuration driver · 003910eb
      Nishanth Menon authored 
      SoC family such as DRA7 family of processors have, in addition
to the regular muxing of pins (as done by pinctrl-single), a separate
hardware module called IODelay which is also expected to be configured.
The "IODelay" module has it's own register space that is independent
of the control module and the padconf register area.

With recent changes to the pinctrl framework, we can now support
this hardware with a reasonably minimal driver by using #pinctrl-cells,
GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS.

It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay reconfiguration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do as little of muxing as absolutely necessary
without I/O isolation (which can only be done in initial stages of
bootloader).

NOTE: with the system wide I/O isolation scheme present in DRA7 SoC
family, it is not reasonable to do stop all I/O operations for every
such pad configuration scheme. So, we will let it glitch when used in
this mode.

Even with the above limitation, certain functionality such as MMC has
mandatory need for IODelay reconfiguration requirements, depending on
speed of transfer. In these cases, with careful examination of usecase
involved, the expected glitch can be controlled such that it does not
impact functionality.

In short, IODelay module support as a padconf driver being introduced
here is not expected to do SoC wide I/O Isolation and is meant for
a limited subset of IODelay configuration requirements that need to
be dynamic and whose glitchy behavior will not cause functionality
failure for that interface.

IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared
to 0x0 at all times, even when configuring Manual IO Timing Modes.
This is done by eliminating the LOCK_BIT=1 setting from Step
of the Manual IO timing Mode configuration procedure. This option
leaves the CFG_* registers unprotected from unintended writes to the
CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured.

This approach is taken to allow for a generic driver to exist in kernel
world that has to be used carefully in required usecases.
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
[tony@atomide.com: updated to use generic pinctrl functions, added
 binding documentation, updated comments]
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      003910eb
  59. 03 Jan, 2017 5 commits
  61. 07 Dec, 2016 1 commit
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