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  1. 26 Jun, 2006 5 commits
  2. 26 Apr, 2006 1 commit
  3. 12 Jan, 2006 2 commits
    • Luiz Fernando Capitulino's avatar
      [PATCH] x86_64: Sparse warnings fix. · 68209407
      Luiz Fernando Capitulino authored
       Fixes the following sparse warnings:
      
      arch/x86_64/kernel/mce_amd.c:321:29: warning: Using plain integer as NULL pointer
      arch/x86_64/kernel/mce_amd.c:410:41: warning: Using plain integer as NULL pointer
      Signed-off-by: default avatarLuiz Capitulino <lcapitulino@mandriva.com.br>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      68209407
    • Andi Kleen's avatar
      [PATCH] x86_64: Add idle notifiers · 95833c83
      Andi Kleen authored
      This adds a new notifier chain that is called with IDLE_START
      when a CPU goes idle and IDLE_END when it goes out of idle.
      The context can be idle thread or interrupt context.
      
      Since we cannot rely on MONITOR/MWAIT existing the idle
      end check currently has to be done in all interrupt
      handlers.
      
      They were originally inspired by the similar s390 implementation.
      
      They have a variety of applications:
      - They will be needed for CONFIG_NO_IDLE_HZ
      - They can be used for oprofile to fix up the missing time
      in idle when performance counters don't tick.
      - They can be used for better C state management in ACPI
      - They could be used for microstate accounting.
      
      This is just infrastructure so far, no users.
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      95833c83
  4. 15 Nov, 2005 1 commit
    • Jacob Shin's avatar
      [PATCH] x86_64: Support for AMD specific MCE Threshold. · 89b831ef
      Jacob Shin authored
      MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
      This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
      The user may interface through sysfs files in order to change the threshold configuration.
      
      bank%d/error_count - reads current error count, write to clear.
      bank%d/interrupt_enable - set/clear interrupt enable.
      bank%d/threshold_limit - read/write the threshold limit.
      
      APIC vector 0xF9 in hw_irq.h.
      5 software defined bank ids in mce.h.
      new apic.c function to setup threshold apic lvt.
      defaults to interrupt off, count enabled, and threshold limit max.
      sysfs interface created on /sys/devices/system/threshold.
      
      AK: added some ifdefs to make it compile on UP
      Signed-off-by: default avatarJacob Shin <jacob.shin@amd.com>
      Signed-off-by: default avatarAndi Kleen <ak@suse.de>
      Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
      89b831ef