- 16 Feb, 2022 29 commits
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Prike Liang authored
Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Prike Liang authored
Set nv_common_ip_block for GC 10.3.7. Signed-off-by:
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Prike Liang authored
Add SMUIO sw function for the new SMUIO block. Signed-off-by:
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Mario Limonciello authored
The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Prike Liang authored
add nbio sw func for the new 7.5.1 nbio block. Signed-off-by:
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Alex Deucher authored
Since this is an existing asic, adjust the code to follow the same logic as previously so the driver state is consistent. No functional change intended. Acked-by:
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Michel Dänzer authored
Even if PSR is allowed for a present GPU, there might be no eDP link which supports PSR. Fixes: 70897848 ("drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Tao Zhou authored
Otherwise gpu reset will be triggered unconditionally in poison consumption. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Changcheng Deng authored
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members" for these cases. The older style of one-element or zero-length arrays should no longer be used. Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arraysReported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Changcheng Deng <deng.changcheng@zte.com.cn> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Roman Li authored
[Why] The previous change: "Add affected crtcs to atomic state for dsc mst unplug" forces modeset on all added crctc regardless whether timing changed or not. Per our implementation of dsc we need modeset only if timing changed. Otherwise dsc can be programmed incorrectly leading to dsc engine hang. [How] During atomic_check pre-compute dsc params. Only set mode_changed if timing is changed. Reviewed-by:
Hersen Wu <hersenwu@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Victor Skvortsov authored
if (!(tmp & flag)) condition will always evaluate to true when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check that address bits are cleared to determine whether the command is complete. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Tested-by:
Bokun Zhang <bokun.zhang@amd.com> Reviewed by: Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by:
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Hersen Wu authored
[why] payload and slot number of display on dsc mst hub will be adjusted when there is change on any display on dsc hub. to monitor dsc enable/disable, pbn change, we need add log. [How] add mst_pbn to dc_dsc_config of dc_crtc_timing. add dsc, pbn, display name within dc_core_enable_stream, dc_core_disable_stream, dc_stream_log Reviewed-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
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Aric Cyr authored
This version brings along the following fixes: -Fixes bugs for dsc mst hub -Enables 29 denial itnerface by default -Fixes dmub outbox notificatoin Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
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Roman Li authored
[Why] When display topology changed on DSC hub we add all crtcs with dsc support to atomic state. Refer to patch:"drm/amd/display: Trigger modesets on MST DSC connectors" However the original implementation may skip crtc if the topology change caused by unplug. That potentially could lead to no-lightup or corruption on DSC hub after unplug event on one of the connectors. [How] Update add_affected_mst_dsc_crtcs() to use old connector state if new connector state has no crtc (undergoes modeset due to unplug) Fixes: 44be939f ("drm/amd/display: Trigger modesets on MST DSC connectors") Reviewed-by:
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Eric Yang authored
Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Eric Yang <Eric.Yang2@amd.com> Tested-by:
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Luben Tuikov authored
Add the "harvest" field to the IP attributes in the IP discovery sysfs visualization, as this field is present in the binary data. At the time of this commit, the harvest data isn't consistently correct in VBIOS, but it is exposed for completeness, in the hopes that VBIOS will be fixed in the future. Cc: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
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Charlene Liu authored
[why] display mapping change will involved pipe power gating on and off. when doing this too fase, sometimes usbc will have no display. check HW status, it is still in pipe power gating. [how] insert polling HW status to make sure the required state reached. also add dal registry key handling. Reviewed-by:
Sung joon Kim <Sungjoon.Kim@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Hersen Wu authored
[why] when unplug 1 dp from dsc mst hub, atomic_check new request dc_state only include info for the unplug dp. this will not trigger re-compute pbn for displays still connected to hub. [how] all displays connected to dsc hub are available in dc->current_state, by comparing dc->current_state and new request from atomic_chceck, it will provide info of displays connected to hub and do pbn re-compute. Reviewed-by:
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Meenakshikumar Somasundaram authored
[Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Evan Quan authored
Add a quirk in sienna_cichlid_ppt.c to fix some OEM SKU specific stability issues. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
MMHUB PG needs to be disabled for Picasso for stability reasons. Signed-off-by:
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Evan Quan authored
Fulfill the implementations for DriverSmuConfig setting on Sienna_Cichlid. Signed-off-by:
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Evan Quan authored
Fulfill the implementations for DriverSmuConfig setting on Navi1x. Signed-off-by:
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Yiqing Yao authored
[why] pm sysfs should be writable in one VF mode as is in passthrough [how] do not remove write access on pm sysfs if device is in one VF mode Fixes: 11c9cc95 ("amdgpu/pm: Make sysfs pm attributes as read-only for VFs") Signed-off-by:
Yiqing Yao <yiqing.yao@amd.com> Reviewed-by:
Monk Liu <Monk.liu@amd.com> Signed-off-by:
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Evan Quan authored
For Some ASICs, with the PMFW default settings, we may see the power consumption reported via metrics table is "Very Erratic". With the socket power alpha filter set as 10/100ms, we can correct that issue. Signed-off-by:
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Alex Deucher authored
This will make it easier to add new firmwares in the future. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Tom Rix authored
Clang static analysis reports this problem amdgpu_ctx.c:616:26: warning: Assigned value is garbage or undefined args->out.pstate.flags = stable_pstate; ^ ~~~~~~~~~~~~~ amdgpu_ctx_stable_pstate can fail without setting stable_pstate. So check. Fixes: 8cda7a4f ("drm/amdgpu/UAPI: add new CTX OP to get/set stable pstates") Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Bas Nieuwenhuizen authored
For DCN3/3.01/3.02 at least these use the fpu. v2: squash in build fix for when DCN is not enabled (Leo) Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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- 14 Feb, 2022 11 commits
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Nicholas Bishop authored
The iMac 12,1 does not use the gmux driver for backlight, so the radeon backlight device is needed to set the brightness. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1838Signed-off-by:
Nicholas Bishop <nicholasbishop@google.com> Signed-off-by:
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Sung Joon Kim authored
[why] In LTTPR non-transparent mode, we need to reset the cached lane settings before performing link training on the next PHY repeater. Otherwise, the cached lane settings will be used for the next clock recovery e.g. VS = MAX (3) which should not be the case according to the DP specs. We expect to use minimum lane settings on each clock recovery sequence. [how] Reset DPCD and HW lane settings on each repeater LT. Set training pattern to 0 for the repeater that failed LT at the proper place. Reviewed-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
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Jonathan Kim authored
SDMA 5.2.x queues are required to be mapped and unmapped from the extended engines. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Jonathan Kim authored
The KFD only unmaps all queues, all dynamics queues or all process queues since RUN_LIST is mapped with all KFD queues. There's no need to provide a single type unmap so remove this option. Signed-off-by:
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Surbhi Kakarya authored
This patch handles the GPU recovery failure in sriov environment by retrying the reset if the first reset fails. To determine the condition of retry, a new macro AMDGPU_RETRY_SRIOV_RESET is added which returns true if failure is due to ETIMEDOUT, EINVAL or EBUSY, otherwise return false.A new macro AMDGPU_MAX_RETRY_LIMIT is used to limit the retry to 2. It also handles the return status in Post Asic Reset by updating the return code with asic_reset_res and eventually return the return code in amdgpu_job_timedout(). Signed-off-by:
Surbhi Kakarya <surbhi.kakarya@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Stanley.Yang authored
print more error info when deferred uncorrectable ras error changed from V1: move Defferred error msg into query uncorrectable error count function. Signed-off-by:Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Yifan Zhang authored
the 2nd parameter should be smu msg type rather than asic msg index. Fixes: 7d38d9dc ("drm/amdgpu: add mode2 reset support for yellow carp") Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
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yipechai authored
drm/amdgpu: Merge amdgpu_ras_late_init/amdgpu_ras_late_fini to amdgpu_ras_block_late_init/amdgpu_ras_block_late_fini 1. Merge amdgpu_ras_late_init to amdgpu_ras_block_late_init. 2. Remove amdgpu_ras_late_init since no ras block calls amdgpu_ras_late_init. 3. Merge amdgpu_ras_late_fini to amdgpu_ras_block_late_fini. 4. Remove amdgpu_ras_late_fini since no ras block calls amdgpu_ras_late_fini. Signed-off-by:
yipechai <YiPeng.Chai@amd.com> Reviewed-by:
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yipechai authored
In order to reduce redundant struct conversion, modify operating sysfs and interrupt function interface parameters. Signed-off-by:
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yipechai authored
Optimize amdgpu_xgmi_ras_late_init/amdgpu_xgmi_ras_fini function code. Signed-off-by:
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yipechai authored
Optimize amdgpu_umc_ras_late_init/amdgpu_umc_ras_fini function code. Signed-off-by:
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