- 05 May, 2016 40 commits
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Rex Zhu authored
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Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
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rezhu authored
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Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by:
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rezhu authored
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Sonny Jiang authored
Ellesmere and Baffin are VCE 3.4 Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Sonny Jiang authored
Ellesmere and Baffin are UVD 6.3 Signed-off-by:
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Flora Cui authored
V2: use gfx_8_0_*.h instead of gfx_8_1_*.h v3: agd: integrate support for gfx info table Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
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Flora Cui authored
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Alex Deucher authored
Fetch the values from atom rather than hardcoding them in the driver. Signed-off-by: -
Flora Cui authored
V2: seperate baffin & ellesmere settings instead of using fiji ones. Signed-off-by:
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Flora Cui authored
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Flora Cui authored
V2: add golden_settings_baffin_a11 instead of reuse golden_settings_fiji_a10 Signed-off-by:
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Alex Deucher authored
Setup the disp clock and dp reference clock. This is now a separate command table on elm/baf compared to older asics. Reviewed-by:
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Alex Deucher authored
SetPixelClock table handles pll divider calculation and spread spectrum setup, so no need to use calculate the dividers and call the ss enable cmd table. Reviewed-by:
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Alex Deucher authored
New PLL scheme on ELM/BAF. v2: squash in pll fix. Plls are part of the phys. Reviewed-by:
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Alex Deucher authored
New uniphy transmitter setup table for elm/baf. Reviewed-by:
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Alex Deucher authored
New digital encoder setup table for elm/baf. Reviewed-by:
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Alex Deucher authored
New version of the SetPixelClock table for elm/baf. The new table calculates the pll dividers and handles spread spectrum calculations and setup. Reviewed-by:
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Alex Deucher authored
New cmd table for ELM/BAF for setting the dispclock or dprefclock. Signed-off-by:
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Alex Deucher authored
update to internal version 893 v2: Pull in gfx_info changes from 898 Reviewed-by:
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Alex Deucher authored
Fixes array overflow on these chips. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Alex Deucher authored
Prerequiste for the next patch which ups the limits. Reviewed-by:
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Alex Deucher authored
Add support for the display configuration on elm/baf. v2: add missing Stoney case Reviewed-by:
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Alex Deucher authored
New asic types for ellesmere and baffin. Reviewed-by:
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Alex Deucher authored
Add register headers for DCE (Display and Composition Engine) 11.2. Reviewed-by:
Ken Wang <Qingqing.Wang@amd.com> Acked-by:
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Bas Nieuwenhuizen authored
Mesa uses a COPY_DATA packet to copy the grid size for indirect dispatches into COMPUTE_USER_DATA_*. Setting those registers with a SET_SH_REG packet is allowed, not allowing them with other packets seems like an oversight. v2: Clarify commit message. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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Christian König authored
Not needed any more. Signed-off-by:
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Christian König authored
This allows us to have small BOs on the LRU before big ones. v2: fix of by one and list corruption bug Signed-off-by:
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Dave Airlie authored
This isn't being used so drop it. Reviewed-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
Chunming Zhou <David1.Zhou@amd.com> Reviewed-by:
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Chunming Zhou authored
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Chunming Zhou authored
we introduced vmid fence, so one hw submission could produce two fences. Signed-off-by:
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Alex Deucher authored
Acked-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
They care common for all sdma 3.0 parts Acked-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
They can be used for other VI parts. Acked-by:
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Alex Deucher authored
v2: just enable MGCG for now since CGCG causes hangs Acked-by:
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Alex Deucher authored
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