- 01 May, 2022 5 commits
-
-
Dmitry Baryshkov authored
Remove additional indirection: specify IRQ callbacks and IRQ indices directly rather than through the pointer in the irq structure. For each IRQ we have a constant IRQ callback. This change simplifies code review as the reader no longer needs to remember which function is called. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/474700/ Link: https://lore.kernel.org/r/20220217043148.480898-6-dmitry.baryshkov@linaro.orgSigned-off-by:
-
Dmitry Baryshkov authored
Get rid of dpu_encoder_helper_register_irq/unregister_irq helpers, call dpu_core_register/unregister_callback directly, without surrounding them with helpers. Reviewed-by:
Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by:
-
Dmitry Baryshkov authored
DPU interrupts code allows multiple callbacks per interrut. In reality none of the interrupts is shared between blocks (and will probably never be). Drop support for registering multiple callbacks per interrupt to simplify interrupt handling code. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
-
Dmitry Baryshkov authored
The argument clear of the function dpu_core_irq_read() is always true. Remove it. Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by:
-
Dmitry Baryshkov authored
Remove extra dpu_irq_* wrappers from dpu_kms.c, merge them directly into dpu_core_irq_* functions. Reviewed-by:
-
- 27 Apr, 2022 2 commits
-
-
Tom Rix authored
Smatch reports this issue msm_ringbuffer.c:43:36: warning: symbol 'msm_sched_ops' was not declared. Should it be static? msm_sched_ops is only used in msm_ringbuffer.c so change its storage-class specifier to static. Signed-off-by:
Tom Rix <trix@redhat.com> Reviewed-by:
-
Abhinav Kumar authored
Remove unused MSM_DISPLAY_CAP_HOT_PLUG and MSM_DISPLAY_CAP_EDID macros from msm_drv.h. Even if we need these, there are drm equivalent ones present. Reported-by:
-
- 25 Apr, 2022 29 commits
-
-
Vinod Koul authored
When DSC is enabled, we need to configure DSI registers accordingly and configure the respective stream compression registers. Add support to calculate the register setting based on DSC params and timing information and configure these registers. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/480934/ Link: https://lore.kernel.org/r/20220406094031.1027376-15-vkoul@kernel.orgSigned-off-by:
-
Vinod Koul authored
Update headers from mesa commit: commit 28ae397be111c37c6ced397e12d453a7695701bd Author: Vinod Koul <vkoul@kernel.org> Date: Fri Apr 1 16:53:04 2022 +0530 freedreno/registers: update dsi registers to support dsc Display Stream compression (DSC) compresses the display stream in host which is later decoded by panel. This requires addition of 3 new DSI registers to support DSC over DSI. Signed-off-by: -
Vinod Koul authored
Add a mode valid callback for dsi_mgr for checking mode being valid in case of DSC. For DSC the height and width needs to be multiple of slice, so we check that here Reviewed-by:
-
Vinod Koul authored
This add the bits in RM to enable the DSC blocks Reviewed-by:
-
Vinod Koul authored
For DSC to work we typically need a 2,2,1 configuration. This should suffice for resolutions up to 4k. For more resolutions like 8k this won't work. Also, it is better to use 2 LMs and DSC instances as half width results in lesser power consumption as compared to single LM, DSC at full width. The panel has been tested only with 2,2,1 configuration, so for now we blindly create 2,2,1 topology when DSC is enabled Co-developed-by:
-
Vinod Koul authored
Somehow documentation for num_dspp was missed, so add that Reviewed-by:
-
Dmitry Baryshkov authored
DPU supports different topologies for the case when multiple INTFs are being driven by the single phys_enc. The driver defaults to using 3DMux in such cases. Don't use it if DSC merge is used instead. Suggested-by:
-
Vinod Koul authored
We need to configure the encoder for DSC configuration and calculate DSC parameters for the given timing so this patch adds that support by adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled. Reviewed-by:
-
Vinod Koul authored
Later gens of hardware have DSC bits moved to hw_ctl, so configure these bits so that DSC would work there as well Reviewed-by:
-
Vinod Koul authored
This adds SDM845 DSC blocks into hw_catalog Reviewed-by:
-
Vinod Koul authored
In SDM845, DSC can be enabled by writing to pingpong block registers, so add support for DSC in hw_pp Reviewed-by:
-
Vinod Koul authored
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add support by adding hw blocks for DSC Reviewed-by:
-
Vinod Koul authored
When DSC is enabled, we need to get the DSC parameters from the panel driver, so add a dsc parameter in panel to fetch and pass DSC configuration for DSI panels to DPU encoder, which will enable and then configure DSC hardware blocks accordingly. Signed-off-by:
-
Vinod Koul authored
Display Stream Compression (DSC) parameters need to be calculated. Add helpers and struct msm_display_dsc_config in msm_drv for this msm_display_dsc_config uses drm_dsc_config for DSC parameters. Reviewed-by:
-
Kuogee Hsieh authored
Widebus feature will transmit two pixel data per pixel clock to interface. This feature now is required to be enabled to easy migrant to higher resolution applications in future. However since some legacy chipsets does not support this feature, this feature is enabled by setting wide_bus_en flag to true within msm_dp_desc struct. changes in v2: -- remove compression related code from timing -- remove op_info from struct msm_drm_private -- remove unnecessary wide_bus_en variables -- pass wide_bus_en into timing configuration by struct msm_dp Changes in v3: -- split patch into 3 patches -- enable widebus feature base on chip hardware revision Changes in v5: -- DP_INTF_CONFIG_DATABUS_WIDEN Changes in v6: -- static inline bool msm_dp_wide_bus_enable() in msm_drv.h Changes in v7: -- add Tested-by Changes in v9: -- add wide_bus_en to msm_dp_desc Changes in v10: -- add wide_bus_en boolean to dp_catalog struc to avoid passing it as parameter Changes in v11: -- add const to dp_catalog_hw_revision() -- add const to msm_dp_wide_bus_available() Changes in v12: -- dp_catalog_hw_revision(const struct dp_catalog *dp_catalog) -- msm_dp_wide_bus_available(const struct msm_dp *dp_display) Signed-off-by:
Kuogee Hsieh <quic_khsieh@quicinc.com> Reported-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
-
Kuogee Hsieh authored
Widebus feature will transmit two pixel data per pixel clock to interface. Timing engine provides driving force for this purpose. This patch base on HPG (Hardware Programming Guide) to revise timing engine register setting to accommodate both widebus and non widebus application. Also horizontal width parameters need to be reduced by half since two pixel data are clocked out per pixel clock when widebus feature enabled. Widebus can be enabled individually at DP. However at DSI, widebus have to be enabled along with DSC to achieve pixel clock rate be scaled down with same ratio as compression ratio when 10 bits per source component. Therefore this patch add no supports of DSI related widebus and compression. Changes in v2: -- remove compression related code from timing -- remove op_info from struct msm_drm_private -- remove unnecessary wide_bus_en variables -- pass wide_bus_en into timing configuration by struct msm_dp Changes in v3: -- split patch into 3 patches Changes in v4: -- rework timing engine to not interfere with dsi/hdmi -- cover both widebus and compression Changes in v5: -- remove supports of DSI widebus and compression Changes in v7: -- split this patch into 3 patches -- add Tested-by Changes in v8: -- move new registers writes under DATA_HCTL_EN features check. Changes in v10: -- add const inside dpu_encoder_is_widebus_enabled() -- drop useless parenthesis please Signed-off-by:
-
Kuogee Hsieh authored
To improve code readability, this patch replace BIT(x) with correspond register bit define string Signed-off-by:
-
Kuogee Hsieh authored
The “DP timing” requires the active region to be defined in the bottom-right corner of the frame dimensions which is different with DSI. Therefore both display_h_end and display_v_end need to be adjusted accordingly. However current implementation has only display_h_end adjusted. Signed-off-by:
-
Dmitry Baryshkov authored
Remove unused field plane_property from struct msm_drm_private. Also drop the enum msm_mdp_plane_property which also becomes unused. Fixes: 7d36db0b ("drm/msm/mdp5: switch to standard zpos property") Signed-off-by:
-
Dmitry Baryshkov authored
There is no point now in storing arrays of creates planes, connectors and encoders. Remove them from struct msm_drm_private. Signed-off-by:
-
Dmitry Baryshkov authored
Rather than manually looping over encoders array, use standard drm_for_each_encoder() macro. Reviewed-by:
-
Dmitry Baryshkov authored
Remove manual removal of DRM modesetting objects, it is done anyway by the drm_mode_config_cleanup() called from msm_drm_uninit(). Other MSM display drivers (MDP4, MDP5) do not manually destroy objects and trust generic code to do it's work. Reviewed-by:
-
Dmitry Baryshkov authored
Add calls to drm_bridge_add()/drm_bridge_remove() DRM bridges created by the driver. This fixes the following warning. WARNING: CPU: 0 PID: 1 at kernel/locking/mutex.c:579 __mutex_lock+0x840/0x9f4 DEBUG_LOCKS_WARN_ON(lock->magic != lock) Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.18.0-rc1-00002-g3054695a0d27-dirty #55 Hardware name: Generic DT based system unwind_backtrace from show_stack+0x10/0x14 show_stack from dump_stack_lvl+0x58/0x70 dump_stack_lvl from __warn+0xc8/0x1e8 __warn from warn_slowpath_fmt+0x78/0xa8 warn_slowpath_fmt from __mutex_lock+0x840/0x9f4 __mutex_lock from mutex_lock_nested+0x1c/0x24 mutex_lock_nested from drm_bridge_hpd_enable+0x2c/0x84 drm_bridge_hpd_enable from msm_hdmi_modeset_init+0xc0/0x21c msm_hdmi_modeset_init from mdp4_kms_init+0x53c/0x90c mdp4_kms_init from msm_drm_bind+0x514/0x698 msm_drm_bind from try_to_bring_up_aggregate_device+0x160/0x1bc try_to_bring_up_aggregate_device from component_master_add_with_match+0xc4/0xf8 component_master_add_with_match from msm_pdev_probe+0x274/0x350 msm_pdev_probe from platform_probe+0x5c/0xbc platform_probe from really_probe.part.0+0x9c/0x290 really_probe.part.0 from __driver_probe_device+0xa8/0x13c __driver_probe_device from driver_probe_device+0x34/0x10c driver_probe_device from __driver_attach+0xbc/0x178 __driver_attach from bus_for_each_dev+0x74/0xc0 bus_for_each_dev from bus_add_driver+0x160/0x1e4 bus_add_driver from driver_register+0x88/0x118 driver_register from do_one_initcall+0x6c/0x334 do_one_initcall from kernel_init_freeable+0x1bc/0x220 kernel_init_freeable from kernel_init+0x18/0x12c kernel_init from ret_from_fork+0x14/0x2c Fixes: 3d3f8b1f ("drm/bridge: make bridge registration independent of drm flow") Reported-by:
-
Dmitry Baryshkov authored
The msm_mdss serves several roles at this moment. It provides IRQ domain used by MDP5 and DPU drivers but it also serves as a component master for both those usecases. MDP4 (which does not have separate MDSS device) is the component master on it's own. Remove this assymmetry and make both MDP5 and DPU component masters too. This removes a need to care about drm/components from msm_mdss driver, removes an mdss pointer from struct msm_drm_private and simplifies the interface between mdp5/dpu and msm_drv. Reviewed-by:
-
Dmitry Baryshkov authored
MSM DRM driver already allows one to compile out the DP or DSI support. Add support for disabling other features like MDP4/MDP5/DPU drivers or direct HDMI output support. Suggested-by:
-
Dmitry Baryshkov authored
Let's make the match's data pointer a (sub-)driver's private data. The only user currently is the msm_drm_init() function, using this data to select kms_init callback. Pass this callback through the driver's private data instead. Reviewed-by:
-
Dmitry Baryshkov authored
Currently the msm platform driver is a multiplex handling several cases: - headless GPU-only driver, - MDP4 with flat device nodes, - MDP5/DPU MDSS with all the nodes being children of MDSS node. This results in not-so-perfect code, checking the hardware version (MDP4/MDP5/DPU) in several places, checking for mdss even when it can not exist, etc. Split the code into three handling subdrivers (mdp4, mdss and headless msm). Reviewed-by:
-
Dmitry Baryshkov authored
Since now there is just one mdss subdriver, drop all the indirection, make msm_mdss struct completely opaque (and defined inside msm_mdss.c) and call mdss functions directly. Reviewed-by:
-
Dmitry Baryshkov authored
MDP5 and DPU1 both provide the driver handling the MDSS region, which handles the irq domain and (incase of DPU1) adds some init for the UBWC controller. Unify those two pieces of code into a common driver. Reviewed-by:
-
- 21 Apr, 2022 4 commits
-
-
Chia-I Wu authored
simple_ondemand interacts poorly with clamp_to_idle. It only looks at the load since the last get_dev_status call, while it should really look at the load over polling_ms. When clamp_to_idle true, it almost always picks the lowest frequency on active because the gpu is idle between msm_devfreq_idle/msm_devfreq_active. This logic could potentially be moved into devfreq core. Fixes: 7c0ffcd4 ("drm/msm/gpu: Respect PM QoS constraints") Signed-off-by:
Chia-I Wu <olvaffe@gmail.com> Cc: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20220416003314.59211-3-olvaffe@gmail.comSigned-off-by:
Rob Clark <robdclark@chromium.org>
-
Chia-I Wu authored
Move tracking and busy time calculation to msm_devfreq_get_dev_status. Signed-off-by:
-
Chia-I Wu authored
It is redundant since commit 7c0ffcd4 ("drm/msm/gpu: Respect PM QoS constraints") because dev_pm_qos_update_request triggers get_dev_status. Signed-off-by:
-
Rob Clark authored
The motivation at this point is mainly native userspace mesa driver in a VM guest. The one remaining synchronous "hotpath" is buffer allocation, because guest needs to wait to know the bo's iova before it can start emitting cmdstream/state that references the new bo. By allocating the iova in the guest userspace, we no longer need to wait for a response from the host, but can just rely on the allocation request being processed before the cmdstream submission. Allocation failures (OoM, etc) would just be treated as context-lost (ie. GL_GUILTY_CONTEXT_RESET) or subsequent allocations (or readpix, etc) can raise GL_OUT_OF_MEMORY. v2: Fix inuse check v3: Change mismatched iova case to -EBUSY Signed-off-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com> Link: https://lore.kernel.org/r/20220411215849.297838-11-robdclark@gmail.comSigned-off-by:
-
