- 30 Mar, 2021 17 commits
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Wei Yongjun authored
Fix the return value check which testing the wrong variable in mt7621_pci_phy_probe(). Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210305034931.3237558-1-weiyongjun1@huawei.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Geert Uytterhoeven authored
Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of ARMADA375_USBCLUSTER_PHY to MACH_ARMADA_375, and ask the user in case of compile-testing. Fixes: eee47538 ("phy: add support for USB cluster on the Armada 375 SoC") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210208150252.424706-1-geert+renesas@glider.beSigned-off-by:
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Yang Li authored
In one of the error paths of the for_each_child_of_node() loop in of_property_read_u32, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/phy/ti/phy-j721e-wiz.c:786:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 795. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1614244674-66556-1-git-send-email-yang.lee@linux.alibaba.comSigned-off-by:
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Sergio Paracuellos authored
When this was rewriten to get mainlined and start to use 'linux/bitfield.h' headers, XTAL_MASK was wrong. It must mask three bits but only two were used. Hence properly fix it to make things work. Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Signed-off-by:
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Swapnil Jakhade authored
Update PCIe + USB register sequences for correct PLL1 clock configuration. Also, update sequences for other USB configurations with dependent changes. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.comSigned-off-by:
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Kishon Vijay Abraham I authored
Update SGMII/QSGMII configuration specific to TI. Signed-off-by:
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Kishon Vijay Abraham I authored
Configure MAC clock dividers required for QSGMII to be functional. Signed-off-by:
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Swapnil Jakhade authored
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was expecting 10GHz clock, configuration was giving 8GHz clock. Update register sequences to get correct PLL1 configuration. Also, update single link PCIe and single link SGMII/QSGMII configurations with related changes. Signed-off-by:
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Kishon Vijay Abraham I authored
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by:
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Kishon Vijay Abraham I authored
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Signed-off-by:
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Kishon Vijay Abraham I authored
commit 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled the internal clocks depending on the subnodes that are populated in device tree. However recent discussions in the mailing list [1] suggested to just add #clock cells in the parent DT node and model the clocks within the driver. Model the mux clocks without device tree input for AM64x SoC. Don't remove the earlier design since DT nodes for J7200 and J721e are already upstreamed. [1] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.orgSigned-off-by:
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Kishon Vijay Abraham I authored
The frequency of the txmclk between PCIe and SERDES has changed to 250MHz from 500MHz. Configure full rate divider for AM64 accordingly. Signed-off-by:
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Kishon Vijay Abraham I authored
commit 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in wiz. However during cleanup, it removed only the MUX clock provider. Remove the DIVIDER clock provider here. Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by:
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Kishon Vijay Abraham I authored
Both "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" are static data that is common for all wiz instances. Including "struct regmap_field" for each of the wiz instances can yield undesirable results. Move "struct regmap_field" out of "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" and make them point to constant data. So far no issues are observed since both these structures are not accessed outside the probe. Signed-off-by:
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Konstantin Porotchkin authored
Add DTS binding for Marvell CP110 UTMI PHY Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210307163343.25684-4-kostap@marvell.comSigned-off-by:
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Konstantin Porotchkin authored
The new file name is marvell,armada-3700-utmi-phy.yaml Signed-off-by:
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Konstantin Porotchkin authored
Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of this driver. Signed-off-by:
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- 25 Mar, 2021 6 commits
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Zhang Yunkai authored
'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Signed-off-by:
Zhang Yunkai <zhang.yunkai@zte.com.cn> Link: https://lore.kernel.org/r/20210319113612.494623-1-zhang.yunkai@zte.com.cnSigned-off-by:
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Bhaskar Chowdhury authored
s/subsytem/subsystem/ Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Link: https://lore.kernel.org/r/20210320204055.26107-1-unixbhaskar@gmail.comSigned-off-by:
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Sandeep Maheswaram authored
Add the compatible string for sc7280 SoC from Qualcomm Signed-off-by:
Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615978901-4202-3-git-send-email-sanm@codeaurora.orgSigned-off-by:
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Chunfeng Yun authored
The phy may be named as pcie-phy when the T-PHY only supports PCIe mode, it's also the similar case for SATA, named as sata-phy. Reviewed-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20210316092232.9806-4-chunfeng.yun@mediatek.comSigned-off-by:
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Chunfeng Yun authored
mt7623-hdmi-tx is compatible to mt2701-hdmi-tx, and the compatible "mediatek,mt7623-hdmi-tx" is not supported in driver, in fact uses "mediatek,mt2701-hdmi-tx" instead on MT7623, so changes the compatible items to make dependence clear. Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by:
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Chunfeng Yun authored
mt7623-mipi-tx is compatible to mt2701-mipi-tx, and use "mediatek,mt2701-mipi-tx" instead on MT7623, so modify the compatible items to make dependence clear. Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Acked-by:
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- 17 Mar, 2021 9 commits
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Steen Hegelund authored
Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G interfaces available in the Sparx5 SoC. Signed-off-by:
Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by:
Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210218161451.3489955-4-steen.hegelund@microchip.comSigned-off-by:
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Steen Hegelund authored
Provide new phy configuration interfaces for media type and speed that allows e.g. PHYs used for ethernet to be configured with this information. Signed-off-by:
Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by:
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Steen Hegelund authored
Document the Sparx5 ethernet serdes phy driver bindings. Signed-off-by:
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Seiya Wang authored
This commit adds dt-binding documentation of UFS M-Phy for Mediatek MT8195 SoC Platform. Signed-off-by:
Seiya Wang <seiya.wang@mediatek.com> Link: https://lore.kernel.org/r/20210316111443.3332-9-seiya.wang@mediatek.comSigned-off-by:
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Seiya Wang authored
This commit adds dt-binding documentation of T-Phy for Mediatek MT8195 SoC Platform. Signed-off-by:
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Vinod Koul authored
TI Serdes changes for 5.13
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Kishon Vijay Abraham I authored
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by:
Peter Rosin <peda@axentia.se> Acked-by:
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Kishon Vijay Abraham I authored
Add binding for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by:
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Kishon Vijay Abraham I authored
Add bindings for AM64 SERDES Wrapper. Signed-off-by:
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- 15 Mar, 2021 7 commits
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Rafał Miłecki authored
On BCM4908 USB PHY is managed using power controller so it needs describing properly using the power-domains. Signed-off-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210309182616.25783-1-zajec5@gmail.comSigned-off-by:
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Rafał Miłecki authored
phy-brcm-usb has some conditional init code required on selected brcmstb devices. Execution of that code depends on family / product detected by brcmstb soc code. For ARCH_BCM4908 brcmstb soc code always return 0 values as ids. Don't bother selecting & compiling that redundant driver. Depends-on: 149ae80b ("soc: bcm: brcmstb: add stubs for getting platform IDs") Signed-off-by:
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Gustavo A. R. Silva authored
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20210305100219.GA142595@embeddedorSigned-off-by:
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Junlin Yang authored
Fix OF node leaks by calling of_node_put in for_each_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by:
Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210216082739.1414-1-angkery@163.comSigned-off-by:
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Junlin Yang authored
Fix OF node leaks by calling of_node_put in for_each_available_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by:
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Amelie Delaunay authored
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by:
Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210208114659.15269-3-amelie.delaunay@foss.st.comSigned-off-by:
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Amelie Delaunay authored
usbphyc provides a unique clock called ck_usbo_48m. STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation. ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by:
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- 12 Mar, 2021 1 commit
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Liam Beguin authored
Start by reading the content of the VENDOR_SPECIFIC2 register and update each bit field based on device properties when defined. The use of bit masks prevents fields from overriding each other and enables users to clear bits which are set by default, like datapolarity in this instance. Signed-off-by:
Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20201211191241.21306-1-liambeguin@gmail.comSigned-off-by:
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