- 02 Feb, 2021 21 commits
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Mikita Lipski authored
[why] Need to unassign DSC from pipes that are not using it so other pipes can acquire it. That is needed for asic's that have unmatching number of DSC engines from the number of pipes. [how] Before acquiring dsc to stream resources, first remove it. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Eryk Brol <Eryk.Brol@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Stylon Wang authored
This reverts commit b24bdc37. It caused memory leak after S3 on 4K HDMI displays. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Anthony Koo authored
[Why] The PWL backlight curve is used by the firmware to convert between brightness and linear PWM value. Driver has a backlight LUT, but the firmware holds a PWL curve and interpolates between points. The calculations are incorrect leading to slightly off backlight values being programmed. [How] Fix the PWL backlight curve threshold/offset calculations Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
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Aric Cyr authored
This DC update brings improvements in multiple areas. In summary, we highlight: - Fix display detection on HDMI ComboPHY - Drop SOC bounding box hookup - Fix DPCD values Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
- Add field for passing line time for a frame Signed-off-by:
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Sung Lee authored
[WHY] When enabling HDMI on ComboPHY, there are not enough clock sources to complete display detection. [HOW] Initialize more clock sources. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Wenjing Liu authored
[why] In HDCP update stream config interface, some variables are named as xxx_supported, but in fact the variable indicates whether or not xxx_enabled. Correct the naming so it is less confusing to read the code. Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
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Lewis Huang authored
[Why] In seamless boot without a flip case, the flag power_gated didn't get cleared when resetting path mode because the plane_state is null. The following sequence will cause this issue: 1. OS call set mode to clone/extended 2. Reset path mode to remove edp [How] Set power gated default to true in seamless boot pipe Signed-off-by:Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
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Bhawanpreet Lakha authored
[Why] Currently we discard the current context and recreate it. The current context is what is applied to the HW so we should be re-using this rather than creating a new context. Recreating the context can lead to mismatch between new context and the current context For example: gsl groups get changed when we create a new context this can cause issues in a multi display config (with flip immediate) because we don't align the existing gsl groups in the new and current context. If we reuse the current context the gsl group assignment stays the same. [How] Instead of discarding the current context, we instead just copy the current state and add/remove planes and streams. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Michael Strauss authored
[WHY] Safeguarding as pointer may be null in diagnostic environment Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Brendan Steve Leder authored
Some dcnxxx__resource.c do not initialize the i2c speed; this patch adds the required initialization at dc_construct(). Signed-off-by:
Brendan Steve Leder <brendanSteve.Leder@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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George Shen authored
[Why] The translation between the DPCD value and the specified AUX_RD_INTERVAL in the DP spec do not match. [How] Update values to match the spec. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] There aren't any ASIC where we use these binaries and they aren't useful for future use since it's inconvenient to extend and maintain these structures. [How] Drop the support from DM and DC for now. Signed-off-by:
Roman Li <Roman.Li@amd.com> Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Christian König authored
Some newer APUs can scanout directly from GTT, that saves us from allocating another bounce buffer in VRAM and enables freesync in such configurations. Without this patch creating a framebuffer from the imported BO will fail and userspace will fall back to a copy. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
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Xiaojian Du authored
This patch is to remove some useless code for vangogh. In the earlier code, vangogh can't finish all the sequence of smu late init. But now vangogh has one stable work state,so remove the useless code. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by:
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Xiaojian Du authored
This patch is to fill in the data member of v2 gpu metrics table for vangogh. Signed-off-by:
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chen gong authored
For Vangogh: The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation. The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation. Signed-off-by:
chen gong <curry.gong@amd.com> Acked-by:
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xinhui pan authored
Flag TTM_PL_FLAG_CONTIGUOUS is only valid for VRAM domain. So fix the false positive by checking memory type too. Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
xinhui pan <xinhui.pan@amd.com> Signed-off-by:
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Ramesh Errabolu authored
drm/amdgpu: Limit the maximum size of contiguous VRAM that can be encapsulated by an instance of DRM memory node [Why] Enable 1:1 mapping between VRAM of a DRM node and a scatterlist node [How] Ensure construction of DRM node to not exceed specified limit Reviewed-by:
Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by:
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Huang Rui authored
In drm_gem_object_free, it will call funcs of drm buffer obj. So kfd_alloc should use amdgpu_gem_object_create instead of amdgpu_bo_create to initialize the funcs as amdgpu_gem_object_funcs. [ 396.231390] amdgpu: Release VA 0x7f76b4ada000 - 0x7f76b4add000 [ 396.231394] amdgpu: remove VA 0x7f76b4ada000 - 0x7f76b4add000 in entry 0000000085c24a47 [ 396.231408] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 396.231445] #PF: supervisor read access in kernel mode [ 396.231466] #PF: error_code(0x0000) - not-present page [ 396.231484] PGD 0 P4D 0 [ 396.231495] Oops: 0000 [#1] SMP NOPTI [ 396.231509] CPU: 7 PID: 1352 Comm: clinfo Tainted: G OE 5.11.0-rc2-custom #1 [ 396.231537] Hardware name: AMD Celadon-RN/Celadon-RN, BIOS WCD0401N_Weekly_20_04_0 04/01/2020 [ 396.231563] RIP: 0010:drm_gem_object_free+0xc/0x22 [drm] [ 396.231606] Code: eb ec 48 89 c3 eb e7 0f 1f 44 00 00 55 48 89 e5 48 8b bf 00 06 00 00 e8 72 0d 01 00 5d c3 0f 1f 44 00 00 48 8b 87 40 01 00 00 <48> 8b 00 48 85 c0 74 0b 55 48 89 e5 e8 54 37 7c db 5d c3 0f 0b c3 [ 396.231666] RSP: 0018:ffffb4704177fcf8 EFLAGS: 00010246 [ 396.231686] RAX: 0000000000000000 RBX: ffff993a0d0cc400 RCX: 0000000000003113 [ 396.231711] RDX: 0000000000000001 RSI: e9cda7a5d0791c6d RDI: ffff993a333a9058 [ 396.231736] RBP: ffffb4704177fdd0 R08: ffff993a03855858 R09: 0000000000000000 [ 396.231761] R10: ffff993a0d1f7158 R11: 0000000000000001 R12: 0000000000000000 [ 396.231785] R13: ffff993a0d0cc428 R14: 0000000000003000 R15: ffffb4704177fde0 [ 396.231811] FS: 00007f76b5730740(0000) GS:ffff993b275c0000(0000) knlGS:0000000000000000 [ 396.231840] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 396.231860] CR2: 0000000000000000 CR3: 000000016d2e2000 CR4: 0000000000350ee0 [ 396.231885] Call Trace: [ 396.231897] ? amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x24c/0x25f [amdgpu] [ 396.232056] ? __dynamic_dev_dbg+0xcd/0x100 [ 396.232076] kfd_ioctl_free_memory_of_gpu+0x91/0x102 [amdgpu] [ 396.232214] kfd_ioctl+0x211/0x35b [amdgpu] [ 396.232341] ? kfd_ioctl_get_queue_wave_state+0x52/0x52 [amdgpu] Fixes: 246cb7e4 ("drm/amdgpu: Introduce GEM object functions") Reviewed-by:
Changfeng <changzhu@amd.com> Signed-off-by:
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Huang Rui authored
We cannot modify initial_domain every time while the retry starts. That will cause the busy waiting that unable to switch to GTT while the vram is not enough. Fixes: f8aab604 ("drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs") Signed-off-by:
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- 01 Feb, 2021 7 commits
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Alex Deucher authored
On some boards the rpm interface apparently does not work at all leading to the fan not spinning or spinning at strange speeds. Both interfaces work properly on the boards I have. Let's try and use the percent interface instead. v2: rebase on revert Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408 Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by:
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Alex Deucher authored
On some boards the rpm interface apparently does not work at all leading to the fan not spinning or spinning at strange speeds. Revert this for now to fix 5.10, 5.11. The follow on patch fixes this properly for 5.12. This reverts commit 8d6e65ad. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408Signed-off-by:
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Abaci Team authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:3137:35-40: WARNING: conversion to bool not needed here Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Suggested-by:
Yang Li <oswb@linux.alibaba.com> Signed-off-by:
Abaci Team <abaci-bugfix@linux.alibaba.com> Signed-off-by:
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Ori Messinger authored
The purpose of this patch is to add a missing device ID for Sienna Cichlid. The missing ID "0x73A1" is now added to the "amdgpu_drv.c" file. Signed-off-by:
Ori Messinger <Ori.Messinger@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Evan Quan authored
Supplement of previous fix. Signed-off-by:
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Matt Coffin authored
Currently, the the input to the pp_od_clk_voltage sysfs interface has two adjacent separator characters, i.e. "\n\0", then we try to parse an argument out of the empty string, whereas we really should just ignore this case, and treat any number of adjacent separators as one separator for arguments. We do this here by simply skipping the argument parsing for all empy-string arguments. An example test case would be `echo 's 1 900' > pp_od_clk_voltage` (note the two spaces after the 's'. This also solves the issue where the written string ends with both a newline, and a nul-terminator, '\n\0', as is the case for `echo 's 1 900' > pp_od_clk_voltage` since the recent rebase. Got lost during code rebase/merge. No need to port this to other branches. Reviewed-by:
Matt Coffin <mcoffin13@gmail.com> Signed-off-by:
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Evan Quan authored
This reverts commit 2456c290. Got lost during code rebase/merge. No need to port this to other branches. Signed-off-by:
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- 28 Jan, 2021 2 commits
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Lang Yu authored
Move all the dummy functions in amdgpu_amdkfd.c to amdgpu_amdkfd.h as inline functions. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Suggested-by:
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Alex Deucher authored
Until the issues in the SMU firmware are fixed. Signed-off-by:
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- 25 Jan, 2021 10 commits
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Mario Kleiner authored
This fixes corrupted display output in HDMI deep color 10/12 bpc mode at least as observed on AMD Mullins, DCE-8.3. It will hopefully also provide fixes for other DCE's up to DCE-11, assuming those will need similar fixes, but i could not test that for HDMI due to lack of suitable hw, so viewer discretion is advised. dce110_stream_encoder_hdmi_set_stream_attribute() is used for HDMI setup on all DCE's and is missing color_depth assignment. dce110_program_pix_clk() is used for pixel clock setup on HDMI for DCE 6-11, and is missing color_depth assignment. Additionally some of the underlying Atombios specific encoder and pixelclock setup functions are missing code which is in the classic amdgpu kms modesetting path and the in the radeon kms driver for DCE6/DCE8. encoder_control_digx_v3() - Was missing setup code wrt. amdgpu and radeon kms classic drivers. Added here, but untested due to lack of suitable test hw. encoder_control_digx_v4() - Added missing setup code. Successfully tested on AMD mullins / DCE-8.3 with HDMI deep color output at 10 bpc and 12 bpc. Note that encoder_control_digx_v5() has proper setup code in place and is used, e.g., by DCE-11.2, but this code wasn't used for deep color setup due to the missing cntl.color_depth setup in the calling function for HDMI. set_pixel_clock_v5() - Missing setup code wrt. classic amdgpu/radeon kms. Added here, but untested due to lack of hw. set_pixel_clock_v6() - Missing setup code added. Successfully tested on AMD mullins DCE-8.3. This fixes corrupted display output at HDMI deep color output with 10 bpc or 12 bpc. Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Reviewed-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Mario Kleiner authored
In set_clamp(), the comments and definitions for the COLOR_DEPTH_101010 and COLOR_DEPTH_121212 cases directly contradict the code comment which explains how this should work, whereas the COLOR_DEPTH_888 case is consistent with the code comments. Comment says the bitmask should be chosen to align to the top-most 10 or 12 MSB's on a 14 bit bus, but the implementation contradicts that: 10 bit case sets a mask for 12 bpc clamping, whereas 12 bit case sets a mask for 14 bpc clamping. Note that during my limited testing on DCE-8.3 (HDMI deep color) and DCE-11.2 (DP deep color), this didn't have any obvious ill effects, neither did fixing it change anything obvious for the better, so this fix may be inconsequential on DCE, and just reduce the confusion of innocent bystanders when reading the code and trying to investigate problems with 10 bpc+ output. Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by:
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Arnd Bergmann authored
clang warns about the -mhard-float command line arguments on architectures that do not support this: clang: error: argument unused during compilation: '-mhard-float' [-Werror,-Wunused-command-line-argument] Move this into the gcc-specific arguments. Fixes: e77165bf ("drm/amd/display: Add DCN3 blocks to Makefile") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Dan Carpenter authored
The debug printk dereferences "link->link_enc" before we have ensured that it is non-NULL. Fix this potential NULL derefence by moving the printk after the check. Fixes: 64ff0882 ("drm/amd/display: Log link/connector info provided in BIOS object table") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Jonathan Gray authored
Change the license of color_table.c to match color_table.h granting permission to modify and distribute. Signed-off-by:
Jonathan Gray <jsg@jsg.id.au> Signed-off-by:
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Colin Ian King authored
Currently the ! operator is incorrectly being used to flip bits on mask values. Fix this by using the bit-wise ~ operator instead. Addresses-Coverity: ("Logical vs. bitwise operator") Fixes: 3c9a7b7d ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3") Reviewed-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Arunpravin authored
store swsmu user power configurations which include power limit, clock frequencies, fan speed and fan mode on suspend and reinstate on resume. V2: Addressed Lijo's review comments added a function to set clock interdependencies add check on fan control mode to reapply fan speed V3: Addressed review comments from Alex moved store logic and reinstate function call into swSMU V4: added a logic to keep off storing configurations in suspend V5: Addressed review comments from Lijo add a restore flag give restore priority to mclk comparing fclk and socclk Signed-off-by:Arunpravin <Arunpravin.PaneerSelvam@amd.com> Acked-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Jingwen Chen authored
[Why] when vram lost happened in guest, try to write vram can lead to kernel stuck. [How] When the readback data is invalid, don't do write work, directly reschedule a new work. Signed-off-by:
Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu<monk.liu@amd.com> Signed-off-by:
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Lang Yu authored
Replace "/" with div_u64 for 32-bit OS. On 32-bit OS, the use of "/" for 64-bit division will cause build error, i.e. "__udivdi3/__divdi3 undefined!". Fixes: ea7154d8 ("drm/amd/display: Update dcn30_apply_idle_power_optimizations() code") Signed-off-by:
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Pratik Vishwakarma authored
This reverts commit 57eeaf47. Original issue of flash line when MPO enabled on idle screen was fixed by raising clocks. This had negative effect of extra power being drained. With the upstream commit 9d03bb10 ("drm/amd/display: disable dcn10 pipe split by default") flash line issue was fixed and had positive effect for battery life. Hence this patch is no more required. Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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