- 12 May, 2016 6 commits
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Andy Shevchenko authored
There is a duplication in the debug messages when accessing SCR registers. Remove duplication to make the messages neat. Tested-by:
Christian Lamparter <chunkeey@googlemail.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Tejun Heo <tj@kernel.org>
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Andy Shevchenko authored
DMA operates with physical addresses which is not exactly the same as ioremap() returns. Introduce variable to keep physical address of the SATA FIFO register and supply it when prepare DMA channel. Tested-by:
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Andy Shevchenko authored
This simplifies error handling and cleanup by using devm to manage IO mappings. Tested-by:
Mans Rullgard <mans@mansr.com> Signed-off-by:
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Mans Rullgard authored
This consolidates the reads from each of the if/else branches to one place making the code a lot nicer to look at. Tested-by:
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Mans Rullgard authored
Rename the register access macros and use standard _relaxed() ops instead of __raw variants with explicit byte swapping. The original driver used the ppc-specific in/out_le32(). When it was adapted to other systems, these were added to the driver under ifdefs. However, those names are not defined as macros on ppc, so it ended up replacing them there as well with altered semantics. This patch restores the original semantics on ppc and makes the accesses no less strict on other systems. Also fixes too many sparse warnings to count. Tested-by:
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Andy Shevchenko authored
Convert dmaengine_terminate_all() calls to synchronous and asynchronous versions where appropriate. Tested-by:
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- 10 May, 2016 16 commits
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Mans Rullgard authored
The pointer to the mmio register base is missing the __iomem annotation. Fix this. Tested-by:
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Mans Rullgard authored
The (void *__iomem) cast is wrong. Change the target type of the "base" pointer to void __iomem instead and drop the cast. Tested-by:
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Mans Rullgard authored
Casting a pointer to unsigned long only to immediately cast it back to a pointer makes no sense. Fix this. Tested-by:
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Mans Rullgard authored
The sata_dwc_qc_prep() does nothing. Use the default ata_noop_qc_prep instead. Tested-by:
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Andy Shevchenko authored
Here we refactor HOSTDEV{P}_FROM_*() macros to fit one line and fix the definition of HSDEV_FROM_HSDEVP() where wrong name of the parameter waas used. Tested-by: -
Mans Rullgard authored
This moves all global data into the driver private struct, thus permitting multiple devices of this type to be used. The core_scr_read/write() functions are replaced with equivalent calls to the existing sata_dwc_scr_read/write(). Tested-by:
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Mans Rullgard authored
This adds support for powering on an optional PHY when activating the device. Tested-by:
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Mans Rullgard authored
Currently this driver only works with a DesignWare DMA engine which it registers manually using the second "reg" address range and interrupt number from the DT node. This patch makes the driver instead use the "dmas" property if present, otherwise optionally falling back on the old way so existing device trees can continue to work. With this change, there is no longer any reason to depend on the 460EX machine type so drop that from Kconfig. Tested-by:
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Andy Shevchenko authored
ata_sff_qc_issue() can't handle DMA commands and thus we have to avoid it for them. Do call ata_bmdma_qc_issue() instead for this case. Note that the former one distinguishes PIO and DMA mode and behaves accordingly. Suggested-by:
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Mans Rullgard authored
Calling dmaengine_prep_slave_sg() for non-dma ATA commands is unnecessary at best and could be harmful if the dma driver reacts badly to this. It also causes this driver to print a bogus error message in these cases. This patch changes sata_dwc_qc_issue() to only do the dma setup for dma commands and also reports an error to libata if if fails. Tested-by:
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Andy Shevchenko authored
There is no need to have a platform driver compiled since the DMA driver is used as a library. Tested-by:
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Andy Shevchenko authored
In the original code the DMA is always a flow controller. Set this accordingly in updated code. Tested-by:
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Andy Shevchenko authored
The burst size as defined by DMAengine API is in items of address width. Derive burst size from AHB_DMA_BRST_DFLT (64 bytes) by dividing it to DMA_SLAVE_BUSWIDTH_4_BYTES (4 bytes) that gives us 16 items. Tested-by:
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Andy Shevchenko authored
The original code states: Make sure a LLI block is not created that will span 8K max FIS boundary. If the block spans such a FIS boundary, there is a chance that a DMA burst will cross that boundary -- this results in an error in the host controller. Since we have switched to generic DMAengine API we satisfy above by setting dma_boundary value to 0x1fff. Suggested-by:
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Christian Lamparter authored
This patch fixes Machine Check "Data Write PLB Error" which happens when libata-sff's ata_sff_dev_select is trying to write into the device_addr in order to select a drive. However, SATA has no master or slave devices like the old ATA Bus, therefore selecting a different drive is kind of pointless. Data Write PLB Error Oops: Machine check, sig: 7 [#1] PowerPC 44x Platform Modules linked in: CPU: 0 PID: 508 Comm: scsi_eh_0 Not tainted 4.6.0-rc3-next-20160412+ #10 [...] NIP [c027e820] ata_sff_dev_select+0x3c/0x44 LR [c027e810] ata_sff_dev_select+0x2c/0x44 Call Trace: [cec31cd0] [c027da00] ata_sff_postreset+0x40/0xb4 (unreliable) [cec31ce0] [c027a03c] ata_eh_reset+0x5cc/0x928 [cec31d60] [c027a840] ata_eh_recover+0x330/0x10bc [cec31df0] [c027bae0] ata_do_eh+0x4c/0xa4 [...] Signed-off-by:
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Mans Rullgard authored
This lock is already taken in ata_scsi_queuecmd() a few levels up the call stack so attempting to take it here is an error. Moreover, it is pointless in the first place since it only protects a single, atomic assignment. Enabling lock debugging gives the following output: ============================================= [ INFO: possible recursive locking detected ] 4.4.0-rc5+ #189 Not tainted --------------------------------------------- kworker/u2:3/37 is trying to acquire lock: (&(&host->lock)->rlock){-.-...}, at: [<90283294>] sata_dwc_exec_command_by_tag.constprop.14+0x44/0x8c but task is already holding lock: (&(&host->lock)->rlock){-.-...}, at: [<902761ac>] ata_scsi_queuecmd+0x2c/0x330 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&(&host->lock)->rlock); lock(&(&host->lock)->rlock); *** DEADLOCK *** May be due to missing lock nesting notation 4 locks held by kworker/u2:3/37: #0: ("events_unbound"){.+.+.+}, at: [<9003a0a4>] process_one_work+0x12c/0x430 #1: ((&entry->work)){+.+.+.}, at: [<9003a0a4>] process_one_work+0x12c/0x430 #2: (&bdev->bd_mutex){+.+.+.}, at: [<9011fd54>] __blkdev_get+0x50/0x380 #3: (&(&host->lock)->rlock){-.-...}, at: [<902761ac>] ata_scsi_queuecmd+0x2c/0x330 stack backtrace: CPU: 0 PID: 37 Comm: kworker/u2:3 Not tainted 4.4.0-rc5+ #189 Workqueue: events_unbound async_run_entry_fn Stack : 90b38e30 00000021 00000003 9b2a6040 00000000 9005f3f0 904fc8dc 00000025 906b96e4 00000000 90528648 9b3336c4 904fc8dc 9009bf18 00000002 00000004 00000000 00000000 9b3336c4 9b3336e4 904fc8dc 9003d074 00000000 90500000 9005e738 00000000 00000000 00000000 00000000 00000000 00000000 00000000 6e657665 755f7374 756f626e 0000646e 00000000 00000000 9b00ca00 9b025000 ... Call Trace: [<90009d6c>] show_stack+0x88/0xa4 [<90057744>] __lock_acquire+0x1ce8/0x2154 [<900583e4>] lock_acquire+0x64/0x8c [<9045ff10>] _raw_spin_lock_irqsave+0x54/0x78 [<90283294>] sata_dwc_exec_command_by_tag.constprop.14+0x44/0x8c [<90283484>] sata_dwc_qc_issue+0x1a8/0x24c [<9026b39c>] ata_qc_issue+0x1f0/0x410 [<90273c6c>] ata_scsi_translate+0xb4/0x200 [<90276234>] ata_scsi_queuecmd+0xb4/0x330 [<9025800c>] scsi_dispatch_cmd+0xd0/0x128 [<90259934>] scsi_request_fn+0x58c/0x638 [<901a3e50>] __blk_run_queue+0x40/0x5c [<901a83d4>] blk_queue_bio+0x27c/0x28c [<901a5914>] generic_make_request+0xf0/0x188 [<901a5a54>] submit_bio+0xa8/0x194 [<9011adcc>] submit_bh_wbc.isra.23+0x15c/0x17c [<9011c908>] block_read_full_page+0x3e4/0x428 [<9009e2e0>] do_read_cache_page+0xac/0x210 [<9009fd90>] read_cache_page+0x18/0x24 [<901bbd18>] read_dev_sector+0x38/0xb0 [<901bd174>] msdos_partition+0xb4/0x5c0 [<901bcb8c>] check_partition+0x140/0x274 [<901bba60>] rescan_partitions+0xa0/0x2b0 [<9011ff68>] __blkdev_get+0x264/0x380 [<901201ac>] blkdev_get+0x128/0x36c [<901b9378>] add_disk+0x3c0/0x4bc [<90268268>] sd_probe_async+0x100/0x224 [<90043a44>] async_run_entry_fn+0x50/0x124 [<9003a11c>] process_one_work+0x1a4/0x430 [<9003a4f4>] worker_thread+0x14c/0x4fc [<900408f4>] kthread+0xd0/0xe8 [<90004338>] ret_from_kernel_thread+0x14/0x1c Fixes: 62936009 ("[libata] Add 460EX on-chip SATA driver, sata_dwc_460ex") Tested-by:
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- 02 May, 2016 4 commits
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Andy Shevchenko authored
We pass struct dw_dma_chip to dw_dma_probe() anyway, thus we may use it to pass a platform data as well. While here, constify the source of the platform data. Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
Vinod Koul <vinod.koul@intel.com>
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Andy Shevchenko authored
Keep the entire platform data in the struct dw_dma. It makes the driver a bit cleaner. Acked-by:
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Andy Shevchenko authored
There several changes are done here: - Convert the property to be in bytes Besides that this is a common practice for such property, the use of a value in bytes much more convenient than handling the encoded one. - Rename data_width to data-width in the device tree bindings The change leaves the support for the old format as well just in case someone will use a newer kernel with an old device tree blob. - While here, replace dwc_fast_ffs() by __ffs() Signed-off-by:
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Andy Shevchenko authored
The value of nr_masters equal to 0 is invalid since this DMA controller has to have at least one master. Check this before we proceed with the rest of properties. Acked-by:
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- 19 Apr, 2016 1 commit
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Christian Lamparter authored
This patch changes the driver to allocate DMA descriptors when needed. This stops memory resources to be wasted and letting them sit idle in the free_list structure when the device doesn't need it... This also solves the problem, that a driver has to guess the number of how many descriptors it needs to allocate in advance. Currently, the dma engine will just fail when put under load by sata_dwc_460ex. Signed-off-by:
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- 13 Apr, 2016 12 commits
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Andy Shevchenko authored
To be sure we have the cyclic transfers already gone we set cdesc to NULL. It will prevent the double free. Signed-off-by:
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Andy Shevchenko authored
Residue is a property of any active descriptor. So, any descriptor may be in different state but residue is a feature of active descriptor. Check if the asked descriptor is active and return proper residue value for it. Signed-off-by:
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Andy Shevchenko authored
We have already dedicated variable for flags, therefore no need to create an additional storage for that. Covert dwc->initialized to use dwc->flags. Signed-off-by:
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Andy Shevchenko authored
We have already dedicated variable for flags, therefore no need to create an additional storage for that. Convert dwc->paused to use dwc->flags. Signed-off-by:
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Andy Shevchenko authored
The code is fixed to satisfy a compiler otherwise we have drivers/dma/dw/core.c: In function ‘dwc_handle_cyclic’: drivers/dma/dw/core.c:568: warning: comparison between signed and unsigned drivers/dma/dw/core.c: In function ‘dw_dma_tasklet’: drivers/dma/dw/core.c:590: warning: comparison between signed and unsigned drivers/dma/dw/core.c: In function ‘dw_dma_off’: drivers/dma/dw/core.c:1103: warning: comparison between signed and unsigned drivers/dma/dw/core.c: In function ‘dw_dma_cyclic_free’: drivers/dma/dw/core.c:1469: warning: comparison between signed and unsigned drivers/dma/dw/core.c: In function ‘dw_dma_probe’: drivers/dma/dw/core.c:1574: warning: comparison between signed and unsigned There is no functional change. Signed-off-by:
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Andy Shevchenko authored
Since struct dw_dma is allocated and regs member is assigned properly we can use standard IO accessors to the DMA registers. Signed-off-by:
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Mans Rullgard authored
The datasheet requires that the LLP_[SD]_EN bits be cleared whenever LLP.LOC is zero, i.e. in the last descriptor of a multi-block chain. Make the driver do this. Signed-off-by:
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Mans Rullgard authored
The LMS field indicates from which master the descriptor is to be read. This patch assumes this is always the same as the memory side in a peripheral transfer which is true for all known systems. Signed-off-by:
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Mans Rullgard authored
If the DMA controller uses a different byte order than the host CPU, the hardware linked list descriptor fields need to be byte-swapped. This patch makes the driver write these fields using the same byte order it uses for mmio accesses to the DMA engine. I do not know if this is guaranteed to always be correct. Signed-off-by:
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Mans Rullgard authored
On some architectures the DMA controller can have two masters connected to different buses and thus access to memory is possible only through one and to peripheral through the other. This patch changes the src and dst master setting to match the direction of the transfer. Signed-off-by:
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Andy Shevchenko authored
The source and destination masters are reflecting buses or their layers to where the different devices can be connected. The patch changes the master names to reflect which one is related to which independently on the transfer direction. The outcome of the change is that the memory data width is now always limited by a data width of the master which is dedicated to communicate to memory. The patch will not break anything since all current users have the same data width for all masters. Though it would be nice to revisit avr32 platforms to check what is the actual hardware topology in use there. It seems that it has one bus and two masters on it as stated by Table 8-2, that's why everything works independently on the master in use. The purpose of the sequential patch is to fix the driver for configuration of more than one bus. The change is done in the assumption that src_master and dst_master are reflecting a connection to the memory and peripheral correspondently on avr32 and otherwise on the rest. Acked-by:
Hans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by:
Mark Brown <broonie@kernel.org> Signed-off-by:
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Andy Shevchenko authored
The commit 89500520 ("dmaengine: dw: apply both HS interfaces and remove slave_id usage") cleaned up the code to avoid usage of depricated slave_id member of generic slave configuration. Meanwhile it broke the master selection by removing important call to dwc_set_masters() in ->device_alloc_chan_resources() which copied masters from custom slave configuration to the internal channel structure. Everything works until now since there is no customized connection of DesignWare DMA IP to the bus, i.e. one bus and one or more masters are in use. The configurations where 2 masters are connected to the different masters are not working anymore. We are expecting one user of such configuration and need to select masters properly. Besides that it is obviously a performance regression since only one master is in use in multi-master configuration. Select masters in accordance with what user asked for. Keep this patch in a form more suitable for back porting. We are safe to take necessary data in ->device_alloc_chan_resources() because we don't support generic slave configuration embedded into custom one, and thus the only way to provide such is to use the parameter to a filter function which is called exactly before channel resource allocation. While here, replase BUG_ON to less noisy dev_warn() and prevent channel allocation in case of error. Fixes: 89500520 ("dmaengine: dw: apply both HS interfaces and remove slave_id usage") Cc: stable@vger.kernel.org Signed-off-by:
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- 26 Mar, 2016 1 commit
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Linus Torvalds authored
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