- 30 Jun, 2022 1 commit
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Srinivasa Rao Mandadapu authored
Fix the compilation error, caused by updating constant variable. Hence remove redundant constant variable, which is no more useful as per new design. The issue is due to some unstaged changes. Fix it up. Fixes: 36fe2684 ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets") Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 28 Jun, 2022 11 commits
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Krzysztof Kozlowski authored
gpio-keys schema requires keys to have more generic name. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220616005333.18491-4-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Nícolas F. R. A. Prado authored
Commit fe44e498 ("pinctrl: mediatek: add rsel setting on mt8192") added RSEL bias type definition for some pins on mt8192. In order to be able to configure the bias on those pins, add the RSEL values in the bias-pull-up and bias-pull-down properties in the binding. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220627173209.604400-1-nfraprado@collabora.comSigned-off-by:
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Krzysztof Kozlowski authored
The Samsung SoC pin controller driver uses only three defines from the bindings header with pin configuration register values, which proves the point that this header is not a proper bindings-type abstraction layer with IDs. Define the needed register values directly in the driver and stop using the bindings header. Signed-off-by:
Chanho Park <chanho61.park@samsung.com> Acked-by:
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Xiang wangx authored
Delete the redundant word 'and'. Signed-off-by:
Xiang wangx <wangxiang@cdjrlc.com> Reviewed-by:
Paul Menzel <pmenzel@molgen.mpg.de> Link: https://lore.kernel.org/r/20220618130854.12321-1-wangxiang@cdjrlc.comSigned-off-by:
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Aidan MacDonald authored
Update the driver to use an immutable IRQ chip to fix this warning: "not an immutable chip, please consider fixing it!" Preserve per-chip labels by adding an ->irq_print_chip() callback. Acked-by:Marc Zyngier <maz@kernel.org> Reviewed-by:
Paul Cercueil <paul@crapouillou.net> Reviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20220622185010.2022515-3-aidanmacdonald.0x0@gmail.comSigned-off-by:
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Aidan MacDonald authored
Instead of accessing ->hwirq directly, use irqd_to_hwirq(). Suggested-by:
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Sai Krishna Potthuri authored
Fix the below kernel-doc warning by adding the description for return value. "warning: No description found for return value of 'zynqmp_pmux_get_function_groups'". Signed-off-by:
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1655462819-28801-5-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.comSigned-off-by:
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Sai Krishna Potthuri authored
Add support to handle 'output-enable' and 'bias-high-impedance' configurations. As part of the output-enable configuration, ZynqMP pinctrl driver takes care of removing the pins from tri-state. Signed-off-by:
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Sai Krishna Potthuri authored
Add 'output-enable' configuration parameter to the properties list. Signed-off-by:
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Sai Krishna Potthuri authored
Add configuration values(enable/disable) for tri-state parameter. Signed-off-by:
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Clément Léger authored
Set PINCTRL_OCELOT config option as a tristate and add MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate information. Moreover, switch from builtin_platform_driver() to module_platform_driver(). Signed-off-by:
Clément Léger <clement.leger@bootlin.com> Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.comSigned-off-by:
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- 27 Jun, 2022 1 commit
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Linus Walleij authored
The idea was right but the code was breaking in next. I assume some unstaged commit was involed. Fix it up. Cc: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Cc: Stephen Boyd <swboyd@chromium.org> Fixes: 36fe2684 ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets") Signed-off-by:
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- 26 Jun, 2022 2 commits
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.20 - Fix reporting of input disabled pins on RZ/G2L.
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Linus Walleij authored
After applying patches I get these warnings: drivers/pinctrl/mediatek/pinctrl-mt8192.c:1302:56: warning: "/*" within comment [-Wcomment] drivers/pinctrl/mediatek/pinctrl-mt8192.c:1362:56: warning: "/*" within comment [-Wcomment] Something is wrong with the missing end-slashes. Add them. Cc: Guodong Liu <guodong.liu@mediatek.com> Cc: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by:
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- 25 Jun, 2022 11 commits
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Guodong Liu authored
Remove pin definitions that do not support the R0 & R1 pinconfig property. Signed-off-by:
Guodong Liu <guodong.liu@mediatek.com> Reviewed-by:
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Guodong Liu authored
Function bias_combo getter/setters already handle all cases advanced drive configuration, include drive for I2C related pins. Signed-off-by:
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Guodong Liu authored
1. I2C pins's resistance value can be controlled by rsel register. This patch provides rsel (resistance selection) setting on mt8192. 2. Also add the missing pull type array for mt8192 to document the pull type of each pin and prevent invalid pull type settings. Signed-off-by:
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Guodong Liu authored
This patch provides the advanced drive raw data setting version for I2C used pins on mt8192. Signed-off-by:
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Guodong Liu authored
1. The dt-binding expects that drive-strength arguments be passed in mA, but the driver was expecting raw values. And that this commit changes the driver so that it is aligned with the binding. 2. This commit provides generic driving setup, which support 2/4/6/8/10/12/14/16mA driving, original driver just set raw data setup setting when use drive-strength property. Signed-off-by:
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Stefan Wahren authored
Commit 6c846d02 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning to indicate if the gpiolib is altering the internals of irqchips. The bcm2835 pinctrl is also affected by this warning. Fix this by making the irqchip in the bcm2835 pinctrl driver immutable. Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
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Stefan Wahren authored
The commit b8a19382 ("pinctrl: bcm2835: Fix support for threaded level triggered IRQs") assigned the irq_mask/unmask callbacks with the already existing functions for irq_enable/disable. The wasn't completely the right way (tm) to fix the issue, because these callbacks shouldn't be identical. So fix this by rename the functions to represent their intension and drop the unnecessary irq_enable/disable assigment. Suggested-by:
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Lukas Bulwahn authored
Maintainers of the directory Documentation/devicetree/bindings/pinctrl are also the maintainers of the corresponding directory include/dt-bindings/pinctrl. Add the file entry for include/dt-bindings/pinctrl to the appropriate section in MAINTAINERS. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613122955.20714-1-lukas.bulwahn@gmail.comSigned-off-by:
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Nikita Travkin authored
GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the function was never assigned to the pingroup (even though the function exists already). Add this mode to the related pins. Fixes: 5373a2c5 ("pinctrl: qcom: Add msm8916 pinctrl driver") Signed-off-by:
Nikita Travkin <nikita@trvn.ru> Link: https://lore.kernel.org/r/20220612145955.385787-4-nikita@trvn.ruSigned-off-by:
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Srinivasa Rao Mandadapu authored
Update lpass lpi pin control driver, with clock optional check for ADSP disabled platforms. This check required for distingushing ADSP based platforms and ADSP bypass platforms. In case of ADSP enabled platforms, where audio is routed through ADSP macro and decodec GDSC Switches are triggered as clocks by pinctrl driver and ADSP firmware controls them. So It's mandatory to enable them in ADSP based solutions. In case of ADSP bypass platforms clock voting is optional as these macro and dcodec GDSC switches are maintained as power domains and operated from lpass clock drivers. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Add boolean param qcom,adsp-bypass-mode to support adsp bypassed sc7280 platforms. Which is required to make clock voting as optional for ADSP bypass platforms. Signed-off-by:
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- 15 Jun, 2022 14 commits
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Krzysztof Kozlowski authored
Reference generic pin controller schema to enforce proper root node name. Signed-off-by:
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Miaoqian Lin authored
of_parse_phandle() returns a node pointer with refcount incremented, we should use of_node_put() on it when not need anymore. Add missing of_node_put() to avoid refcount leak." Fixes: c2f6d059 ("pinctrl: nomadik: refactor DT parser to take two paths") Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220607111602.57355-1-linmq006@gmail.comSigned-off-by:
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Linus Walleij authored
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Samuel Holland authored
None of the sunxi pin controllers have a module reset line. This is confirmed by documentation (A80) as well as experimentation (A33). Since the property is not applicable to any variant of the hardware, let's remove it from the binding. Signed-off-by:
Samuel Holland <samuel@sholland.org> Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220531053623.43851-4-samuel@sholland.orgSigned-off-by:
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Samuel Holland authored
None of the sunxi pin controllers have a module reset line. This is confirmed by documentation (A80) as well as experimentation (A33). Let's remove the inaccurate properties. Signed-off-by:
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Samuel Holland authored
None of the sunxi pin controllers have a module reset line. All of the SoC documentation, where available, agrees. The bits that would be used for the PIO reset (i.e. matching the order of the clock gate bits) are always reserved, both in the CCU and in the PRCM. And experiments on several SoCs, including the A33, confirm that those reserved bits indeed have no effect. Let's remove this superfluous code and dependency, and also remove the include statement that was copied to the other r_pio drivers. Signed-off-by:
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Nícolas F. R. A. Prado authored
Commit cafe19db ("pinctrl: mediatek: Backward compatible to previous Mediatek's bias-pull usage") allowed the bias-pull-up and bias-pull-down properties to be used for setting PUPD/R1/R0 type bias on mtk-paris based SoC's, which was previously only supported by the custom mediatek,pull-up-adv and mediatek,pull-down-adv properties. Since the bias-pull-{up,down} properties already have defines associated thus being more descriptive and is more universal on MediaTek platforms, and given that there are no mediatek,pull-{up,down}-adv users on mt8192 yet, remove the custom adv properties in favor of the generic ones. Note that only mediatek,pull-up-adv was merged in the binding, but not its down counterpart. Fixes: edbacb36 ("dt-bindings: pinctrl: mt8192: Add mediatek,pull-up-adv property") Signed-off-by:
AngeloGioacchino Del Regno <angelogiocchino.delregno@collabora.com> Reviewed-by:
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Nícolas F. R. A. Prado authored
Commit e5fabbe4 ("pinctrl: mediatek: paris: Support generic PIN_CONFIG_DRIVE_STRENGTH_UA") added support for using drive-strength-microamp instead of mediatek,drive-strength-adv. Since there aren't any users of mediatek,drive-strength-adv on mt8192 yet, remove this property and add drive-strength-microamp in its place, which has a clearer meaning. Fixes: 4ac68333 ("dt-bindings: pinctrl: mt8192: Add mediatek,drive-strength-adv property") Signed-off-by:
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Basavaraj Natikar authored
Provide pinmux functionality by implementing pinmux_ops. Signed-off-by:
Basavaraj Natikar <Basavaraj.Natikar@amd.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220601152900.1012813-7-Basavaraj.Natikar@amd.comSigned-off-by:
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Basavaraj Natikar authored
Presently there is no way to change pinmux configuration run time. Hence add a function to get IOMUX resource which can be used to configure IOMUX GPIO pins run time. Signed-off-by:
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Basavaraj Natikar authored
AMD pingroup can be extended to support multi-function pins. Hence define and use a macro "AMD_PINS" to represent larger number of pins. Signed-off-by:
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Basavaraj Natikar authored
AMD pingroup can be extended to support multi-function pins. Hence use PINCTRL_PINGROUP to manage and represent larger number of pingroups inline. Signed-off-by:
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Basavaraj Natikar authored
Remove 'struct amd_pingroup' and instead use 'struct pingroup'. Signed-off-by:
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Basavaraj Natikar authored
Add 'struct pingroup' to represent pingroup and 'PINCTRL_PINGROUP' macro for inline use. Both are used to manage and represent larger number of pingroups. Signed-off-by:
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