- 29 Nov, 2022 40 commits
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Dillon Varone authored
[Description] Output transfer function must be programmed per pipe as part of a front end update when the plane changes, or output transfer function changes for a given plane. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
Jasdeep Dhillon <jdhillon@amd.com> Signed-off-by:
Dillon Varone <Dillon.Varone@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Dillon Varone authored
[Description] Calculations for determining DCC meta size should be pitch*height*bpp/256. Reviewed-by:
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Dillon Varone authored
[Description] Need to subtract unused section of the viewport when calculating required space in MALL for subvp instead of adding, to prevent over allocation. Reviewed-by:
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Alvin Lee authored
[Description] - When entering into a SubVP config that requires a minimal transition we need to retain phantom pipes and also restore the mall config - This is because the min transition will remove phantom pipes from the context (shallow copy) and not restore it's original state - This is just a workaround, and needs a proper fix Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Alvin Lee authored
[Description] - This is a workaround to avoid concurrency issues -- a fast update creates a shallow copy of the dc current_state, and removes all subvp/phantom related flags. - We want to prevent the fast update thread from removing those flags in case there's another thread running that requires the info for proper programming Reviewed-by:
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Dmytro Laktyushkin authored
The 'commit 52e4fdf09ebc ("drm/amd/display: use low clocks for no plane configs")' introduced a change that set low clock values for DCN31 and DCN32. As a result of these changes, DC started to spam the log with the following warning: ------------[ cut here ]------------ WARNING: CPU: 8 PID: 1486 at drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dccg.c:58 dccg2_update_dpp_dto+0x3f/0xf0 [amdgpu] [..] CPU: 8 PID: 1486 Comm: kms_atomic Tainted: G W 5.18.0+ #1 RIP: 0010:dccg2_update_dpp_dto+0x3f/0xf0 [amdgpu] RSP: 0018:ffffbbd8025334d0 EFLAGS: 00010206 RAX: 00000000000001ee RBX: ffffa02c87dd3de0 RCX: 00000000000a7f80 RDX: 000000000007dec3 RSI: 0000000000000000 RDI: ffffa02c87dd3de0 RBP: ffffbbd8025334e8 R08: 0000000000000001 R09: 0000000000000005 R10: 00000000000331a0 R11: ffffffffc0b03d80 R12: ffffa02ca576d000 R13: ffffa02cd02c0000 R14: 00000000001453bc R15: ffffa02cdc280000 [..] dcn20_update_clocks_update_dpp_dto+0x4e/0xa0 [amdgpu] dcn32_update_clocks+0x5d9/0x650 [amdgpu] dcn20_prepare_bandwidth+0x49/0x100 [amdgpu] dcn30_prepare_bandwidth+0x63/0x80 [amdgpu] dc_commit_state_no_check+0x39d/0x13e0 [amdgpu] dc_commit_streams+0x1f9/0x3b0 [amdgpu] dc_commit_state+0x37/0x120 [amdgpu] amdgpu_dm_atomic_commit_tail+0x5e5/0x2520 [amdgpu] ? _raw_spin_unlock_irqrestore+0x1f/0x40 ? down_trylock+0x2c/0x40 ? vprintk_emit+0x186/0x2c0 ? vprintk_default+0x1d/0x20 ? vprintk+0x4e/0x60 We can easily trigger this issue by using a 4k@120 or a 2k@165 and running some of the kms_atomic tests. This warning is triggered because the per-pipe clock update is not happening; this commit fixes this issue by ensuring that DPPCLK is updated when calculating the watermark and dlg is invoked. Fixes: 2641c7b7 ("drm/amd/display: use low clocks for no plane configs") Reported-by:Mark Broadworth <mark.broadworth@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] This fix was intended for improving on coding style but in the process uncovers a race condition, which explains why we are getting incorrect length in DPIA AUX replies. Due to the call path of DPIA AUX going from DC back to DM layer then again into DC and the added complexities on top of current DC AUX implementation, a proper fix to rely on current dc_lock to address the race condition is difficult without a major overhual on how DPIA AUX is implemented. [How] - Add a mutex dpia_aux_lock to protect DPIA AUX transfers - Remove DMUB_ASYNC_TO_SYNC_ACCESS_* codes and rely solely on aux_return_code_type for error reporting and handling - Separate SET_CONFIG from DPIA AUX transfer because they have quiet different processing logic - Remove unnecessary type casting to and from void * type Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Stylon Wang <stylon.wang@amd.com> Signed-off-by:
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Dillon Varone authored
[Description] MALL SS allocation calculations should iterate over all pipes to determine the the allocation size required for HW cursor. Reviewed-by:
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Aric Cyr authored
This version brings along following fixes: -Program output transfer function when required -Fix arthmetic errror in MALL size caluclations for subvp -DCC Meta pitch used for MALL allocation -Debugfs entry to tell if connector is DPIA link -Use largest vready_offset in pipe group -Fixes race condition in DPIA Aux transfer Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Signed-off-by:
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Wesley Chalmers authored
[WHY] Corruption can occur in LB if vready_offset is not large enough. DML calculates vready_offset for each pipe, but we currently select the top pipe's vready_offset, which is not necessarily enough for all pipes in the group. [HOW] Wherever program_global_sync is currently called, iterate through the entire pipe group and find the highest vready_offset. Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
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Xiongfeng Wang authored
As comment of pci_get_class() says, it returns a pci_device with its refcount increased and decreased the refcount for the input parameter @from if it is not NULL. If we break the loop in radeon_atrm_get_bios() with 'pdev' not NULL, we need to call pci_dev_put() to decrease the refcount. Add the missing pci_dev_put() to avoid refcount leak. Fixes: d8ade352 ("drm/radeon: handle non-VGA class pci devices with ATRM") Fixes: c61e2775 ("drm/radeon: split ATRM support out from the ATPX handler (v3)") Signed-off-by:
Xiongfeng Wang <wangxiongfeng2@huawei.com> Signed-off-by:
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Dan Carpenter authored
We re-arranged this code recently so "ret" is always zero at this point. Signed-off-by:
Dan Carpenter <error27@gmail.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Yu Songping authored
The logical operator '&&' will make smu->ppt_funcs->set_gfx_power_up_by_imu segment fault when smu->ppt_funcs is NULL. Signed-off-by:
Yu Songping <yusongping@huawei.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Yushan Zhou authored
release_firmware() checks whether firmware pointer is NULL. Remove the redundant NULL check in psp_sw_fini(). Signed-off-by:
Yushan Zhou <katrinzhou@tencent.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Veerabadhran Gopalakrishnan authored
Corrected the typo in the 4K resolution parameters. Fixes: b3a24461 ("amdgpu/nv.c - Added codec query for Beige Goby") Fixes: 9075096b ("amdgpu/nv.c - Optimize code for video codec support structure") Fixes: 9ac0edaa ("drm/amdgpu: add vcn_4_0_0 video codec query") Signed-off-by:
Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Liang He authored
In amdgpu_get_xgmi_hive(), we should not call kfree() after kobject_put() as the PUT will call kfree(). In amdgpu_device_ip_init(), we need to check the returned *hive* which can be NULL before we dereference it. Signed-off-by:
Liang He <windhl@126.com> Reviewed-by:
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Tim Huang authored
Enable PSP FW loading for PSP IP v13.0.11 Signed-off-by:
Tim Huang <tim.huang@amd.com> Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Saleemkhan Jamadar authored
This enable VCN PG, CG and JPEG PG, CG Signed-off-by:
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Yifan Zhang authored
this patch is to enable nbio support for NBIO v7.7.1. Signed-off-by:
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Tim Huang authored
The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use the different mailbox register offset. So use the specific mailbox registers offset for v13.0.4. Signed-off-by:
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Tim Huang authored
Set the default reset method to mode2 for SMU IP v13.0.11 Signed-off-by:
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Yifan Zhang authored
Enable the SMU IP v13.0.11 GFXOFF control Signed-off-by:
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Yifan Zhang authored
this patch to add smu 13 support for smu 13.0.11. Signed-off-by:
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Yifan Zhang authored
Add the entry to set the ppt functions for SMU IP v13.0.11. Signed-off-by:
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Yifan Zhang authored
Add initial support for GC 11.0.4 in KFD compute driver. Signed-off-by:
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Yifan Zhang authored
Add gmc v11 support for GC 11.0.4. Signed-off-by:
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Yifan Zhang authored
Add common soc21 ip block support for GC 11.0.4. Signed-off-by:
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Yifan Zhang authored
this patch to add GC 11.0.4 gfx support to gfx11 implementation. Signed-off-by:
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Yifan Zhang authored
Set the APU flag appropriately for GC 11.0.4. Signed-off-by:
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Yifan Zhang authored
this patch is to set GC 11.0.4 family. Signed-off-by:
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Tim Huang authored
Add PSP IP v13.0.11 ip discovery support. Signed-off-by:
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Yifan Zhang authored
this patch is to enable mes for GC 11.0.4. Signed-off-by:
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Yifan Zhang authored
Enable gfx v11 for GC 11.0.4. Signed-off-by:
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Yifan Zhang authored
Enable gmc (graphic memory controller) v11 for GC 11.0.4. Signed-off-by:
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Yifan Zhang authored
Enable soc21 common for GC 11.0.4. Signed-off-by:
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Likun Gao authored
vram_usagebyfirmware v2_2 is only used in SRIOV case, skip the related settings in bare-metal case currently. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Guchun Chen authored
Add an explicit printing to tell when finishing rpm execution in amdgpu. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Guchun Chen authored
After executing BACO exit, driver needs to poll the status to ensure FW has completed BACO exit sequence to prevent timing issue. v2: use usleep_range to replace msleep to fix checkpatch.pl warnings Signed-off-by:
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Guchun Chen authored
Return true early if ASIC is in BACO state already, no need to talk to SMU. It can fix the issue that driver was not calling BACO exit at all in runtime pm resume, and a timing issue leading to a PCI AER error happened eventually. Fixes: 8795e182 ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()") Suggested-by:
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Tong Liu01 authored
For vram_usagebyfirmware_v2_2, fw_vram_reserve is not used. So fw_vram_usage_va is NULL, and cannot do virt data exchange anymore. Should add drv_vram_usage_va to do virt data exchange in vram_usagebyfirmware_v2_2 case. And refine some code style checks in pre add vram reservation logic patch Signed-off-by:
Tong Liu01 <Tong.Liu01@amd.com> Acked-by:
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