- 11 Jan, 2023 15 commits
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Krzysztof Kozlowski authored
The Always On Subsystem (AOSS) QMP is not a power domain controller since commit 13578045 ("arm64: dts: qcom: sc7180: Use QMP property to control load state") and few others. In fact, it was never a power domain controller but rather control of power state of remote processors. This power state control is now handled differently, thus the AOSS QMP nodes do not have power-domain-cells: sc7280-idp.dtb: power-controller@c300000: '#power-domain-cells' is a required property From schema: Documentation/devicetree/bindings/power/power-domain.yaml AOSS QMP is an interface to the actuall AOSS subsystem responsible for some of power management functions, thus let's call the nodes as "power-management". Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213101921.47924-4-krzysztof.kozlowski@linaro.org
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Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 14abf8df ("arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280") Signed-off-by:
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Krzysztof Kozlowski authored
The SPMI bus uses two address cells and zero size cells (second reg entry - SPMI_USID - is not the size): spmi@c440000: #address-cells:0:0: 2 was expected Fixes: 0f9dc5f0 ("arm64: dts: qcom: sc7180: Add SPMI PMIC arbiter device") Signed-off-by:
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Shazad Hussain authored
Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to get pcie 2a controller enabled on Qdrive3. This patch enables 4GB 64bit memory space for PCIE_2A to have BAR allocations of 64bit pref mem needed on this Qdrive3 platform with dual SoCs for root port and switch NT-EP. Hence this ranges property is overridden in sa8540p-ride.dts only. Moved tlmm node at the end as it tends to become rahter long. Link: https://lore.kernel.org/lkml/Y49k1k8ayI9%2FrK+R@hovoldconsulting.com/Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> Reviewed-by:
Brian Masney <bmasney@redhat.com> Signed-off-by:
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Krzysztof Kozlowski authored
Order top-level nodes like memory, reserved-memory, opp-table-cpu alphabetically for easier code maintenance. No functional change (same dtx_diff, except phandle changes). Signed-off-by:
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Krzysztof Kozlowski authored
Order top-level nodes like memory, reserved-memory, opp-table-cpu alphabetically for easier code maintenance. No functional change (same dtx_diff). Signed-off-by:
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Rob Herring authored
'arm,kryo' is not documented and is not an Arm Ltd thing either as that is Qualcomm branding. The correct compatible is 'qcom,kryo'. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Konrad Dybcio authored
Nagara devices use the Dialog SLG51000 PMIC for powering some camera sensors. Add the required nodes to support it. Signed-off-by:
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Konrad Dybcio authored
Enable the power and volume up buttons, connected to PON and RESIN respectively. Signed-off-by:
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Konrad Dybcio authored
Set up gpio-controlled fixed regulators for camera on PDX223 and fix up the existing ones in common and PDX224 trees. Signed-off-by:
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Konrad Dybcio authored
With PMIC GPIOs now available, set up required pin settings and add gpio-keys. Signed-off-by:
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the PDX223&224 DTSIs to better document the hardware. Diff between 223 and 224: pm8350b < "CAM_PWR_LD_EN", > "NC", pm8350c < "RGBC_IR_PWR_EN", > "NC", Which is due to different camera power wiring on 223 and lack of a ToF sensor on 224. Signed-off-by:
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Konrad Dybcio authored
Now that SPMI is finally in place, include the DTSIs of PMICs present on Nagara. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Vinod Koul authored
Add the spmi bus as found in the SM8450 SoC Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list] Signed-off-by:
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- 10 Jan, 2023 21 commits
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Neil Armstrong authored
Add the QCE and Crypto BAM DMA nodes. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
Add the I2C Master Hub wrapper and I2C serial engines nodes. Signed-off-by:
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Abel Vesa authored
Add dts file for Qualcomm MTP platform which uses SM8550 SoC. Co-developed-by:
Abel Vesa <abel.vesa@linaro.org> Reviewed-by:
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Neil Armstrong authored
Add nodes for PMR735d in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PMK8550 in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550vs in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550ve in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550b in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for PM8550 in separate dtsi file. Signed-off-by:
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Neil Armstrong authored
Add nodes for pm8010 in separate dtsi file. Signed-off-by:
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Abel Vesa authored
Add base dtsi for SM8550 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, interconnect, thermal sensor, cpu cooling maps and SMMU nodes which helps boot to shell with console on boards with this SoC. Co-developed-by:
Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the TCSR clock binding, to gain the Devicetree include file.
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Abel Vesa authored
Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by:
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Bjorn Andersson authored
Merge branch 'icc-sm8550-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.3 Merge the immutable SM8550 interconnect branch, to gain the include file from the binding.
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Dmitry Baryshkov authored
Add silicon specific compatible qcom,sm8450-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8450 against the yaml documentation. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
Add silicon specific compatible qcom,sm8150-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8150 against the yaml documentation. Signed-off-by:
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Krzysztof Kozlowski authored
Each board should define pin drive/bias for used busses. All boards using SPI0 (db845c and cheza) already do it, so drop the bias/drive strength from SoC DTSI. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Krzysztof Kozlowski authored
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by:
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Krzysztof Kozlowski authored
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: dd6459a0 ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts") Reported-by:
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Krzysztof Kozlowski authored
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: 89a32a4e ("arm64: dts: qcom: db845c: add analog audio support") Reported-by:
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Quentin Schulz authored
The reset line is active low for the Goodix touchscreen controller so let's fix the polarity in the Device Tree node. Signed-off-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com> Tested-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
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- 02 Jan, 2023 4 commits
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Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8350-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8250-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: -
Krzysztof Kozlowski authored
Bindings expect power domains to follow generic naming pattern: sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by:
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