- 02 Jul, 2024 12 commits
-
-
André Draszik authored
Some versions of this IP have been integrated using separate PMU power control registers for the HS and SS parts. One example is the Google Tensor gs101 SoC. Such SoCs can now set pmu_offset_usbdrd0_phy_ss in their exynos5_usbdrd_phy_drvdata for the SS phy to the appropriate value. The existing 'usbdrdphy' alias can not be used in this case because that is meant for determining the correct PMU offset if multiple distinct PHYs exist in the system (as opposed to one PHY with multiple isolators). Signed-off-by:
André Draszik <andre.draszik@linaro.org> Tested-by:
Will McVicker <willmcvicker@google.com> Reviewed-by:
Peter Griffin <peter.griffin@linaro.org> Tested-by:
Vinod Koul <vkoul@kernel.org>
-
André Draszik authored
Add a dedicated google,gs101-usb31drd-phy compatible for Google Tensor gs101 SoC. It needs additional clocks enabled for register access, and additional memory regions (PCS & PMA) are required for successful configuration. It also requires various power supplies (regulators) for the internal circuitry to work. The required voltages are: * pll-supply: 0.85V * dvdd-usb20-supply: 0.85V (+10%, -7%) * vddh-usb20-supply: 1.8V (+10%, -7%) * vdd33-usb20-supply: 3.3V (+10%, -7%) * vdda-usbdp-supply: 0.85V * vddh-usbdp-supply: 1.8V Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
-
Miaoqian Lin authored
of_phy_put is used for of_phy_get to release the reference count. Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20240626080911.203630-1-linmq006@gmail.comSigned-off-by:
-
Changhuang Liang authored
We actually want to calculate the alignment values first, then use the alignment value to look up the data from reg_configs[]. Fixes: d3ab7955 ("phy: starfive: Add mipi dphy tx support") Reviewed-by:
Shengyang Chen <shengyang.chen@starfivetech.com> Signed-off-by:
Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20240627020059.163535-1-changhuang.liang@starfivetech.comSigned-off-by:
-
Sean Anderson authored
Add support for printing some basic status information to debugfs. This is helpful when debugging phy consumers to make sure they are configuring the phy appropriately. Signed-off-by:
Sean Anderson <sean.anderson@linux.dev> Link: https://lore.kernel.org/r/20240628205540.3098010-6-sean.anderson@linux.devSigned-off-by:
-
Sean Anderson authored
Take the phy mutex in xlate to protect against concurrent modification/access to gtr_phy. This does not typically cause any issues, since in most systems the phys are only xlated once and thereafter accessed with the phy API (which takes the locks). However, we are about to allow userspace to access phys for debugging, so it's important to avoid any data races. Signed-off-by:
-
Sean Anderson authored
For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by:
-
Sean Anderson authored
The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by:
-
Sean Anderson authored
Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Fixes: 25d70083 ("phy: xilinx: phy-zynqmp: dynamic clock support for power-save") Signed-off-by:
-
Ma Ke authored
cdns_torrent_dp_set_power_state() does not consider that ret might be overwritten. Add return value check of regmap_read_poll_timeout() after register read in cdns_torrent_dp_set_power_state(). Fixes: 5b16a790 ("phy: cadence-torrent: Reorder few functions to remove function declarations") Signed-off-by:
Ma Ke <make24@iscas.ac.cn> Reviewed-by:
Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240702032042.3993031-1-make24@iscas.ac.cnSigned-off-by:
-
Liu Jing authored
The word 'swtich' is wrong, so fix it. Signed-off-by:
Liu Jing <liujing@cmss.chinamobile.com> Link: https://lore.kernel.org/r/20240701112517.6597-1-liujing@cmss.chinamobile.comSigned-off-by:
-
Cristian Ciocaltea authored
Compile testing configurations without REGMAP support enabled results in a bunch of errors being reported: ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:569:21: error: variable ‘rk_hdptx_phy_regmap_config’ has initializer but incomplete type 569 | static const struct regmap_config rk_hdptx_phy_regmap_config = { | ^~~~~~~~~~~~~ ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:570:10: error: ‘const struct regmap_config’ has no member named ‘reg_bits’ 570 | .reg_bits = 32, | ^~~~~~~~ Note that selecting REGMAP alone is not enough, because of the following liker error: phy-rockchip-samsung-hdptx.c:(.text+0x10c): undefined reference to `__devm_regmap_init_mmio_clk' Instead of the obvious fix to enable REGMAP_MMIO, select MFD_SYSCON, which implicitly enables REGMAP_MMIO as well. The rationale is that the driver has been already relying on the syscon functionality. Moreover, without MFD_SYSCON enabled, the test coverage is reduced, since the linker might not detect any potential undefined references following syscon_regmap_lookup_by_phandle() invocation in rk_hdptx_phy_probe() body. That is because the function would unconditionally return -ENOTSUP, hence the compiler is free to optimize out any unreachable code. Finally ensure PHY_ROCKCHIP_SAMSUNG_HDPTX depends on HAS_IOMEM, as required by MFD_SYSCON. Fixes: 553be283 ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by:Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240629-rk-hdptx-compile-test-fix-v1-1-c86675ba8070@collabora.comSigned-off-by:
-
- 20 Jun, 2024 3 commits
-
-
Lorenzo Bianconi authored
Introduce support for Airoha PCIe PHY controller available in EN7581 SoC. Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by:
Zhengping Zhang <zhengping.zhang@airoha.com> Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20ac99aa8628d97778594f606681db7f868f24fe.1718485860.git.lorenzo@kernel.orgSigned-off-by:
-
Lorenzo Bianconi authored
Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY controller. Reviewed-by:
-
Nathan Chancellor authored
In various configurations/architectures, bitfield.h may not be transitively included, which results in a compiler error because FIELD_PREP is an unexpanded macro: drivers/phy/freescale/phy-fsl-imx8qm-hsio.c:459:8: error: call to undeclared function 'FIELD_PREP'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] 459 | val = FIELD_PREP(HSIO_MODE_MASK, val); | ^ 1 error generated. Include bitfield.h explicitly to fix the build. Fixes: 82c56b6d ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support") Signed-off-by:Nathan Chancellor <nathan@kernel.org> Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202406170340.7mk3WU3Q-lkp@intel.com/Reviewed-by:
Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20240620-phy-fsl-imx8qm-hsio-add-bitfield-include-v1-1-5c7c09ed87e6@kernel.orgSigned-off-by:
-
- 15 Jun, 2024 7 commits
-
-
Richard Zhu authored
Add i.MX8QM HSIO PHY driver support. i.MX8QM HSIO has three lane PHY instances, and can be bound to the following controllers in the different use cases listed in below table. - two lanes capable PCIEA controller. - one lane PCIEB controller. - AHCI SATA controller. i.MX8QM HSIO PHYs support the following use cases. +----------------------------------------------------+ | | Lane0| Lane1| Lane2| |-------------------------------|------|------|------| | use case 1: PCIEAX2SATA | PCIEA| PCIEA| SATA | |-------------------------------|------|------|------| | use case 2: PCIEAX2PCIEB | PCIEA| PCIEA| PCIEB| |-------------------------------|------|------|------| | use case 3: PCIEAPCIEBSATA | PCIEA| PCIEB| SATA | +----------------------------------------------------+ Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by:
-
Richard Zhu authored
Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at initialization according to board design. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/1716962565-2084-2-git-send-email-hongxing.zhu@nxp.comSigned-off-by:
-
Shengyang Chen authored
Add mipi dphy tx support for the StarFive JH7110 SoC. It is a module which is used to receive data from DSI driver and transfer data to DSI interface like mipi screen. Signed-off-by:
-
Shengyang Chen authored
StarFive SoCs like the jh7110 use a MIPI D-PHY TX controller based on a M31 IP. Add a binding for it. Signed-off-by:
-
Herman van Hazendonk authored
Adds qcom,usb-hs-phy-msm8660 compatible Used by HP Touchpad (tenderloin) for example. Signed-off-by:
Herman van Hazendonk <github.com@herrie.org> Reviewed-by:
Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240417065454.3599824-1-github.com@herrie.orgSigned-off-by:
-
Dmitry Baryshkov authored
There is no need to specify exact name for the second (AUX) output clock. It has never been used for the lookups based on the system clock name. Partially revert commit 72bea132 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs"), returning compatibility with the existing device tree: reduce clock-output-names to always contain a single entry. Fixes: 72bea132 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs") Acked-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-2-730d1811acf4@linaro.orgSigned-off-by:
-
Dmitry Baryshkov authored
Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9cc ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
-
- 12 Jun, 2024 9 commits
-
-
Neil Armstrong authored
On newer SoCs, the USB2 PHY can require a power-domain to operate, add it as optional. Signed-off-by:
-
Jeff Johnson authored
make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb2.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/phy/broadcom/phy-bcm-ns-usb3.o Add the missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by:
Jeff Johnson <quic_jjohnson@quicinc.com> Link: https://lore.kernel.org/r/20240608-md-drivers-phy-broadcom-v1-1-f070f84cc3f0@quicinc.comSigned-off-by:
-
Jan Kiszka authored
Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com> Link: https://lore.kernel.org/r/60089a71-dad2-4a87-a304-a738e3334d4a@siemens.comSigned-off-by:
-
Josua Mayer authored
Armada CP110 UTMI supports swapping D+ and D- signals. usb251xb.yaml already describes a suitable device-tree property for the same purpose but as child usb controller node. Add optional swap-dx-lanes device-tree property to armada cp110 utmi phy with same semantics as usb251xb: The property lists all ports that swap D+ and D-, unlisted ports are considered correct. Signed-off-by:
Josua Mayer <josua@solid-run.com> Reviewed-by:
-
André Draszik authored
While commit 255ec387 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with the frequency of the reference clock for the USB2.0 phy instead. I stumbled across this while adding support for the Google Tensor gs101, but this should apply to E850 just the same. Do so. Signed-off-by:
-
André Draszik authored
Using 0x82 seems odd, where everything else is just a sequence. On E850, this macro isn't used (as a register value), only to assign its value to the 'extrefclk' variable, which is otherwise unused on that platform. Older platforms don't appear to support 26MHz in the first place (since this macro was added for E850). Furthermore, the downstream driver uses 0x82 to denote USBPHY_REFCLK_DIFF_26MHZ (whatever that means exactly), but for all the other values we match downstream's non-DIFF macros. Update to avoid confusion. No functional change intended. Signed-off-by:
-
André Draszik authored
on / not on is just a boolean flag and is a bit misleading as currently on==1 means to turn off the power, and on==0 to turn power on. Rename the flag and make it a bool to avoid confusion of future readers of this code. No functional change. While at it, fix a whitespace issue in nearby comment. No functional change. Signed-off-by:
-
André Draszik authored
The timers-howto recommends using usleep_range() and friends anytime waiting for >= ~10us is required. Doing so can help the timer subsystem a lot to coalesce wakeups. Additionally, fsleep() exists as a convenient wrapper so we do not have to think about which exact sleeping function is required in which case. Convert all udelay() calls in this driver to use fsleep() to follow the recommendataion. Signed-off-by:
-
André Draszik authored
Most of the macros are ordered high -> low, but there are some outliers. Order them all uniformly from high to low. This will allow adding additional register (field) definitions in a consistent way. While at it, also remove some extra empty lines to group register bit field definitions together with the relevant register. This makes the registers easier to distinguish visually. No functional change. Signed-off-by:
-
- 03 Jun, 2024 9 commits
-
-
devi priya authored
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Co-developed-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.comSigned-off-by:
-
devi priya authored
Add missing register offsets for PCS V5 registers. Reviewed-by:
-
devi priya authored
Add missing register offsets for Qserdes PLL. Reviewed-by:
-
devi priya authored
Document the QMP PCIe PHYs on IPQ9574 platform. Acked-by:
-
Dr. David Alan Gilbert authored
'miphy_initval' is unused since the original commit 2c14e9be ("phy: miphy28lp: Provide support for the MiPHY28lp Generic PHY"). Remove it. Signed-off-by:
Dr. David Alan Gilbert <linux@treblig.org> Link: https://lore.kernel.org/r/20240527205844.165279-1-linux@treblig.orgSigned-off-by:
-
Dr. David Alan Gilbert authored
'regval' is unused since the original commit f8aa6608 ("phy: starfive: Add mipi dphy rx support"). Remove it. Signed-off-by:
-
Bjorn Andersson authored
The SC8180X platform has two UNIPHY blocks, add support for these in the QMP driver. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
-
Bjorn Andersson authored
The SC8180X has two USB3 UNIPHY QMP blocks, add a compatible for these. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240525-sc8180x-usb-mp-v1-1-60a904392438@quicinc.comSigned-off-by:
-
Thomas Richard authored
Add suspend and resume support. The already_configured flag is cleared during the suspend stage to force the PHY initialization during the resume stage. Co-developed-by:
Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by:
Thomas Richard <thomas.richard@bootlin.com> Link: https://lore.kernel.org/r/20240412-j7200-phy-s2r-v1-8-f15815833974@bootlin.comSigned-off-by:
-
