- 28 May, 2019 40 commits
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Stuart Summers authored
In the GETPARAM ioctl handler, use a local variable to consolidate usage of SSEU runtime info. v2: add const to sseu_dev_info variable Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by:
Stuart Summers <stuart.summers@intel.com> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190524154022.13575-2-stuart.summers@intel.com
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Ville Syrjälä authored
Leave a hint in dmesg when we reject a configuration attempting to use C8 planes without the legacy LUT loaded. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190513133904.20374-3-ville.syrjala@linux.intel.comReviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Ville Syrjälä authored
When the first C8 plane gets enabled, or the last one gets disabled we may need to enable/disable the pipe gamma for the other active planes. Check for that and run through the normal intel_color_check() path. Signed-off-by:
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Chris Wilson authored
An old optimisation to reduce the number of atomics per batch sadly relies on struct_mutex for coordination. In order to remove struct_mutex from serialising object/context closing, always taking and releasing an active reference on first use / last use greatly simplifies the locking. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-15-chris@chris-wilson.co.uk
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Chris Wilson authored
Rename the engine this HW context is currently active upon (that we are flying upon) to disambiguate between the mixture of different active terms (and prevent conflict in future patches). Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-14-chris@chris-wilson.co.uk
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Chris Wilson authored
Continuing the decluttering of i915_gem.c by moving the client self throttling into its own file. Signed-off-by:
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Chris Wilson authored
Continuing the decluttering of i915_gem.c by moving the object busy checking into its own file. Signed-off-by:
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Chris Wilson authored
Continuing the decluttering of i915_gem.c by moving the object wait decomposition into its own file. Signed-off-by:
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Chris Wilson authored
Use the per-object local lock to control the cache domain of the individual GEM objects, not struct_mutex. This is a huge leap forward for us in terms of object-level synchronisation; execbuffers are coordinated using the ww_mutex and pread/pwrite is finally fully serialised again. Signed-off-by:
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Chris Wilson authored
Out scatterlist utility routines can be pulled out of i915_gem.h for a bit more decluttering. v2: Push I915_GTT_PAGE_SIZE out of i915_scatterlist itself and into the caller. Signed-off-by:
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Chris Wilson authored
Continuing the theme of separating out the GEM clutter. Signed-off-by:
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Chris Wilson authored
Continuing the decluttering of i915_gem.c, that of the read/write domains, perhaps the biggest of GEM's follies? Signed-off-by:
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Chris Wilson authored
Continuing the decluttering of i915_gem.c, now the turn of do_mmap and the faulthandlers Signed-off-by:
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Chris Wilson authored
Continuing the decluttering of i915_gem.c, this time the legacy physical object. Signed-off-by:
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Chris Wilson authored
Split the plain old shmem object into its own file to start decluttering i915_gem.c v2: Lose the confusing, hysterical raisins, suffix of _gtt. Signed-off-by:
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Chris Wilson authored
Currently the code for manipulating the pages on an object is still residing in i915_gem.c, move it to i915_gem_object.c Signed-off-by:
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Chris Wilson authored
Declutter i915_drv/gem.h by moving the ioctl API into its own header. Signed-off-by:
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Chris Wilson authored
For convenience in avoiding inline spaghetti, keep the type definition as a separate header. Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by:
Jani Nikula <jani.nikula@intel.com> Acked-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-1-chris@chris-wilson.co.uk
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Chris Wilson authored
It was moved over to gt/ but the backmerge brought it back from the dead. Signed-off-by:
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Uma Shankar authored
Attach HDR metadata property to connector object. v2: Rebase v3: Updated the property name as per updated name while creating hdr metadata property v4: Added platform check as suggested by Ville. Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
Shashank Sharma <shashank.sharma@intel.com> Reviewed-by:
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Uma Shankar authored
Added state readout for DRM infoframe and enabled state validation for DRM infoframe. v2: Addressed Ville's review comments and dropped the unused drm infoframe read at intel_hdmi_init. v3: Removed a redundant platform check as per Ville's comment. Signed-off-by:
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Uma Shankar authored
Enable writing of HDR metadata infoframe to panel. The data will be provid by usersapace compositors, based on blending policies and passsed to driver through a blob property. v2: Rebase v3: Fixed a warning message v4: Addressed Shashank's review comments v5: Rebase. Added infoframe calculation in compute config. v6: Addressed Shashank's review comment. Added HDR metadata support from GEN10 onwards as per Shashank's recommendation. v7: Addressed Shashank's review comments v8: Added Shashank's RB. v9: Addressed Ville's review comments. v10: Removed a redundant check as core already handles it, as per Ville's comment. v11: Added the metadata available check to avoid failure in compute_config. Signed-off-by:
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Ville Syrjälä authored
This patch enables infoframes on GLK+ to be used to send HDR metadata to HDMI sink. v2: Addressed Shashank's review comment. v3: Addressed Shashank's review comment. v4: Added Shashank's RB. v5: Dropped hdr_metadata_change check while modeset, as per Ville's suggestion. v6: Removed an unused and duplicate bit defintion, as per Ville's comment. Signed-off-by:
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Uma Shankar authored
BYT/CHT doesn't support DRM Infoframe. This caused a WARN_ON due to a missing CASE while executing intel_hdmi_infoframes_enabled function. This patch fixes the same. Signed-off-by:
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Uma Shankar authored
This patch enables modeset whenever HDR metadata needs to be updated to sink. v2: Addressed Shashank's review comments. v3: Added Shashank's RB. v4: Addressed Ville's review comments. v5: Addressed Ville's review comments. Signed-off-by:
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Michal Wajdeczko authored
Define HuC firmware version for Icelake. v2: 8.4.3238 is now available Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Tony Ye <tony.ye@intel.com> Reviewed-by:
Tony Ye <tony.ye@intel.com> Signed-off-by:
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Michal Wajdeczko authored
Define GuC firmware version for Icelake. Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:
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Michal Wajdeczko authored
Gen11 GuC firmware expects H2G command messages to be sent over CTB (command transport buffers). Signed-off-by:
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Michal Wajdeczko authored
Current GuC firmwares identify response message in a different way. v2: update comments for other H2G bits (Daniele) Signed-off-by:
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Oscar Mateo authored
Starting Gen11 GuC shares interrupt registers with SG unit instead of PM. But for now we don't care about SG interrupts. v2: (Chris) v3: rebased (Michal) v4: more bspec pages, use macros, update commit msg (Michal Wi) Bspec: 19820, 19840, 19841, 20176 Signed-off-by:
Oscar Mateo <oscar.mateo@intel.com> Signed-off-by:
Michał Winiarski <michal.winiarski@intel.com> Signed-off-by:
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Oscar Mateo authored
Controlling and handling of the GuC interrupts is Gen specific. Create virtual functions to avoid redundant runtime Gen checks. Gen-specific versions of these functions will follow. v2: move vfuncs to struct guc (Daniele) v3: rebased Signed-off-by:
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Michal Wajdeczko authored
Gen11 defines new register for checking HuC authentication status. Look into the right register and bit. v2: use reg/mask/value instead of dedicated functions (Daniele) BSpec: 19686 Signed-off-by:
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Michal Wajdeczko authored
Gen11 adds new set of scratch registers that can be used for MMIO based Host-to-Guc communication. Due to limited number of these registers it is expected that host will use them only for command transport buffers (CTB) communication setup if one is available. Bspec: 21044 Signed-off-by:
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Michal Wajdeczko authored
Gen11 defines new more flexible Host-to-GuC interrupt register. Now the host can write any 32-bit payload to trigger an interrupt and GuC can additionally read this payload from the register. Current GuC firmware ignores the payload so we just write 0. Bspec: 21043 Signed-off-by:
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Michal Wajdeczko authored
Define HuC firmware version for Geminilake. Signed-off-by:
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Michal Wajdeczko authored
Define GuC firmware version for Geminilake. Signed-off-by:
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Michal Wajdeczko authored
With newer GuC firmware it is always ok to ask GuC to update power domain states. Make it an unconditional initialization step. Signed-off-by:
John Spotswood <john.a.spotswood@intel.com> Signed-off-by:
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Michal Wajdeczko authored
GuC stores some data in there, which might be stale after a reset. Reinitialize whole ADS in case any part of it was corrupted during previous GuC run. v2: s/reinit/init, update functions descriptions (Tomek/Michal) v3: reset ADS right before fw upload Signed-off-by:
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Michal Wajdeczko authored
New GuC 32.0.3 firmware made many changes around its ABI that require driver updates: * FW release version numbering schema now includes patch number * FW release version encoding in CSS header * Boot parameters * Suspend/resume protocol * Sample-forcewake command * Additional Data Structures (ADS) This commit is a squash of patches 3-8 from series [1]. [1] https://patchwork.freedesktop.org/series/58760/Signed-off-by:
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Michal Wajdeczko authored
Due to the upcoming changes to the GuC ABI interface, we must disable GuC submission mode until final ABI will be available on all GuC firmwares. To avoid regressions on systems configured to run with no longer supported configuration "enable_guc=3" or "enable_guc=1" clear GuC submission bit. v2: force switch to non-GuC submission mode v3: use GEM_BUG_ON (Joonas) Signed-off-by:
Martin Peres <martin.peres@linux.intel.com> Signed-off-by:
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