- 17 Jan, 2023 37 commits
-
-
Mario Limonciello authored
There is already a "default" case in the switch block, so there is no need to have a break after the switch block. Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Christian König authored
We need to reset this or otherwise run into list corruption later on. Fixes: e44a0fe6 ("drm/amdgpu: rework reserved VMID handling") Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Candice Li <candice.li@amd.com> Signed-off-by:
-
YiPeng Chai authored
[Why]: Amdgpu ras uses amdgpu_ras_is_supported to check whether the ras block supports the ras function. amdgpu_ras_is_supported uses .ras_enabled to determine whether the ras function of the block is enabled. But for special asic with mem ecc enabled but sram ecc not enabled, some ras blocks support poison mode but their ras function is not enabled on .ras_enabled, these ras blocks will run abnormally. [How]: If the ras block is not supported on .ras_enabled but the asic supports poison mode and the ras block has ras configuration, it can be considered that the ras block supports ras function. Signed-off-by:YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
YiPeng Chai authored
[Why]: For special asic with mem ecc enabled but sram ecc not enabled, some ras blocks can register their ras configuration to ras list, but these ras blocks are not enabled on .ras_enabled, so it can not get ras block object using amdgpu_ras_get_ras_block. [How]: Remove ras block support check. Even if the ras block checked is not in the ras list, it will return a null pointer and will have no effect. Signed-off-by:
-
YiPeng Chai authored
Perform gpu reset after gfx finishes processing ras poison consumption on gfx_v11_0_3. V2: Move gfx poison consumption handler from hw_ops to ip function level. V3: Adjust the calling position of amdgpu_gfx_poison_consumation_handler. V4: Since gfx v11_0_3 does not have .hw_ops instance, the .hw_ops null pointer check in amdgpu_ras_interrupt_poison_consumption_handler needs to be adjusted. Signed-off-by:
-
YiPeng Chai authored
V2: Optimize gfx_v11_0_set_cp_ecc_error_state function. V3: Define macro constant for me pipe instance address interval. V5: Register and handle gfx cp ecc error irq on gfx v11_0_3. V6: Remove invalid intermediate function call. Signed-off-by:
-
YiPeng Chai authored
Add gfx ras poison consumption irq handling on gfx v11_0_3. V2: Move ras poison consumption irq handling code of gfx v11_0_3 to gfx_v11_0_3.c. V5: Create dedicated irq handler for RLC_GC_FED_INTERRUPT. V6: Remove invalid function call. Signed-off-by: -
YiPeng Chai authored
V2: Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register offset and shift masks. Signed-off-by:
-
YiPeng Chai authored
Add gfx ras function on gfx v11_0_3. V2: 1. Add separate source files for gfx v11_0_3. 2. Create a common function to initialize gfx ras block. V3: 1. Rename amdgpu_gfx_ras_block_init to amdgpu_gfx_ras_sw_init. 2. Adjust the calling position of amdgpu_gfx_ras_sw_init. 3. Remove gfx_v11_0_3_ras_ops. V4: Revert changes in amdgpu_ras_interrupt_poison_consumption_handler. V5: 1. Remove invalid include file in gfx_v11_0_3.c. 2. Reduce the number of parameters of amdgpu_gfx_ras_sw_init. Signed-off-by:
-
Mario Limonciello authored
The existing codebase never had a case for detecting MP0 version on Renoir and instead relied upon hardcoded chip name. This was missed as part of the changes to migrate all IP blocks to build filenames from `amdgpu_ucode.c`. Consequently, Renoir tries to fetch a binary with 11_0_3 in the filename and since it's supposed to have "renoir" in the filename fails to probe. The fbdev still works though so the series worked. Add a case for Renoir into the legacy table to ensure the right ASD and TA firmware load again. Reported-by:
Ekene Akuneme <Ekene.Akuneme@amd.com> Reported-by:
Nicholas Choi <Nicholas.Choi@amd.com> Cc: Alex Hung <Alex.Hung@amd.com> Fixes: 994a9744 ("drm/amd: Parse both v1 and v2 TA microcode headers using same function") Fixes: 54a3e032 ("drm/amd: Add a legacy mapping to "amdgpu_ucode_ip_version_decode"") Signed-off-by:
-
Aric Cyr authored
This version brings along following fixes: - Revert patches that caused regressions associated with audio and an old change that checks the DCN version. - Refactor DDC and HDP. - Move DPIA and DPCD logic to new files. - Updates to DMUB. - Optimization and bug fixes for SUBVP/DRR. - Drop legacy code. Tested-by:
Daniel Wheeler <Daniel.Wheeler@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
-
hersen wu authored
[Why] incorrect skip when drm_connector.index = 0 within event_property_validate and update [How] handle hdcp validate and update for connector 0 Tested-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
hersen wu <hersenxs.wu@amd.com> Signed-off-by:
-
hersen wu authored
[why] For MST topology with 1 physical link and multiple connectors (>=2), e.g. daisy cahined MST + SST, or 1-to-multi MST hub, if userspace set to enable the HDCP simultaneously on all connected outputs, the commit tail iteratively call the hdcp_update_display() for each display (connector). However, the hdcp workqueue data structure for each link has only one DM connector and encryption status members, which means the work queue of property_validate/update() would only be triggered for the last connector within this physical link, and therefore the HDCP property value of other connectors would stay on DESIRED instead of switching to ENABLED, which is NOT as expected. [how] Use array of AMDGPU_DM_MAX_DISPLAY_INDEX for both aconnector and encryption status in hdcp workqueue data structure for each physical link. For property validate/update work queue, we iterates over the array and do similar operation/check for each connected display. Tested-by:
-
Dillon Varone authored
[WHY?] Cannot only consider the MALL required from top pipes because of the MPO case. [HOW?] Only count a pipe if it fits the following criteria: 1) does not have a top pipe (is the topmost pipe for that plane) 2) it does have a top pipe, but that pipe is associated with a different plane Tested-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
Dillon Varone <Dillon.Varone@amd.com> Signed-off-by:
-
Alvin Lee authored
Enable subvp on specifically 1440p@60hz displays even though it can switch in vactive. Tested-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by:
-
Alvin Lee authored
[Description] - Request min clocks after disabling pipes on init - This optimizes for power savings during init sequence - Also handles the case where we boot up with no display connected Tested-by:
-
Brandon Syu authored
[Why] There is an issue mapping non-allocated location of memory. It would allocate gpio registers from an array out of bounds. [How] Patch correct numbers of bounds for using. Tested-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Brandon Syu <Brandon.Syu@amd.com> Signed-off-by:
-
Tony Tascioglu authored
[Why] When an eDP panel is powered externally from a different GPU, we can avoid waiting for hardware sequencing delays when switching the backlight on/off as the display backlight is no longer powered by the original source. [How] This commit extends the 'link_powered_externally' variable to allow bypassing hardware delays for additional backlight commands and force the backlight on/off when a link is powered by another GPU. Tested-by:
Felipe Clark <felipe.clark@amd.com> Acked-by:
Tony Tascioglu <tony.tascioglu@amd.com> Signed-off-by:
-
Charlene Liu authored
keep dig_fifo enable for test pattern generation. Tested-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Signed-off-by:
-
Dillon Varone authored
[WHY?] For dcn32, SMU handles DISPCLK dentist programming. [HOW?] Only use calls to SMU to set DISPCLK. Tested-by:
-
Saaem Rizvi authored
[Why] DCC meta was found to be detached from usable pixel data. Due to this DCC meta and the end of the fetched part of the frame will be on not be on the same mblk. Furthermore if the meta is not aligned to the mblk size, then we require an extra mblk in MALL to account for this. [How] Always add an additional mblk when DCC is enabled for detachment and misalignment. Tested-by:
Saaem Rizvi <SyedSaaem.Rizvi@amd.com> Signed-off-by:
-
Dillon Varone authored
When using freesync on desktop, need to set freesync active bit for AMD VSDBv3 infopacket. Tested-by:
-
Rodrigo Siqueira authored
Remove some code that is never used from freesync file. Tested-by:
-
Tony Tascioglu authored
[Why] When an eDP panel is powered externally by a different GPU, we don't need to wait for hardware sequencing delays when powering down a link, as the display is not dependent on the GPU being powered down. [How] This commit adds a variable 'link_powered_externally' to indicate when a link is being powered by another GPU. Tested-by:
-
Aurabindo Pillai authored
Checking for disabled master pipe on a timing synchronized pipe is incorrect in the case of ODM combine. This case is acceptable as long as the disabled master pipe is part of the ODM tree. Skip printing error message if this condition holds true. Tested-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
-
Aurabindo Pillai authored
This reverts commit e81b6a44. Reverting to put in a better solution which does not involve checking DCN version. Tested-by:
-
Wenjing Liu authored
Tested-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
-
Wenjing Liu authored
Tested-by:
-
Wenjing Liu authored
[why] Extract dp link training logic out to their own files. link_dp_training - high level training sequence and helper functions. link_dp_training_8b_10b - dp1.x training link_dp_training_auxless - aux-less training link_dp_traininig_dpia - dpia training link_dp_training_fixed_vs_pe_retimer - fixed vs pe retimer training link_dp_training_128b_132b - dp2.1 training Tested-by:
-
Saaem Rizvi authored
Current implementation of SubVP does not support cases where stream timing matched neither the destination rect nor the source rect. Will need to further debug to see how we can support these cases. Tested-by:
-
Bhawanpreet Lakha authored
[why] HDCP 1.4 failed on SL8800 SW w/a test driver use. [how] slower down the HW i2c speed when used by HW i2c. Tested-by:
-
Dillon Varone authored
Remove array size on array passed to CalculateDETSwathFillLatencyHiding. Tested-by:
-
Dillon Varone authored
MALL SS and Subvp use the same calculations for determining the size of the required allocation for a given surface, which is already done in DML. Add an interface to extract this information from VBA variables and use in their respective helper functions. Also refactor existing code to remove stale workarounds. Tested-by:
-
Dillon Varone authored
DML does not explicitly consider support for space in MALL required for subvp phantom pipes. This adds a check to make sure portion of phantom surface can fit in MALL. Tested-by:
-
Dillon Varone authored
DML incorrectly uses surface width for determining DCC meta size in MALL allocation calculations. Meta pitch should be used instead. Tested-by:
-
Dillon Varone authored
Two issues existed: 1) Configs that support DRR, but have it disabled will fail subvp+vblank validation incorrectly. Use subvp+vblank path for this case. 2) Configs that support DRR and have it enabled can use higher voltage level than required if they also support subvp+vblank. Use lowest supported voltage level for this case. Tested-by:
-
Dan Carpenter authored
This tab was deleted accidentally and triggers a Smatch warning: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:1006 gfx_v8_0_init_microcode() warn: inconsistent indenting Add it back. Fixes: 0aaafb73 ("drm/amd: Use `amdgpu_ucode_*` helpers for GFX8") Signed-off-by:Dan Carpenter <error27@gmail.com> Signed-off-by:
-
- 13 Jan, 2023 3 commits
-
-
Charlene Liu authored
Required by display init, also update get_dig_mode Tested-by:
Hansen Dsouza <hansen.dsouza@amd.com> Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
-
Mustapha Ghaddar authored
[WHY] Last PR missed name of a struct to match in DMUB [HOW] Update the logic in dmub_cmh.h header Tested-by:
Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by:
Mustapha Ghaddar <mghaddar@amd.com> Signed-off-by:
-
Yifan Zha authored
[Why] SDMA0_CNTL and MMHUB system aperture related registers are blocked by L1 Policy. Therefore, they cannot be accessed by VF and loged in violation. [How] For MMHUB registers, they will be programmed by PF. So VF will skip to program them in mmhubv3_0. For SDMA0_CNTL which is a PF_only register, VF don't need to program it in sdma_v6_0. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Acked-by:
-
