- 11 Oct, 2007 40 commits
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Ralf Baechle authored
Loading ELF binaries based on the section table is totally wrong. This still leaves the other fat bug of referencing symbols in an executable unfixed, so people better don't run strip on their binaries ... As added bonus the new loader is also 23 lines shorter. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Franck Bui-Huu authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
Dump the generated code for clear/copy page calls like it is done for TLB fault handlers. Useful for debugging. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
It's same as cobalt_machine_halt(). Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
It's only used in arch/mips/cobalt/reset.c. Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
They're only used in arch/mips/cobalt/console.c. Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
These PCI definitions are only used in arch/mips/pci/fixup-cobalt.c. Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Florian Fainelli authored
Signed-off-by:
Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
Add LED support to cobalt_defconfig. Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
Add Cobalt Qube series front LED support to platform register. Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Yoichi Yuasa authored
Signed-off-by:
Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
On MP configurations it's highly dubious what this code will actually affect since blasting away cachelines may or may not do the right thing wrt. cache coherency. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Franck Bui-Huu authored
-msym32 and previously the strategy to tell the compiler to generate 64-bit code but the assembler to put it into 32-bit ELF was initially a hack to get around the lack of proper 64-bit binutils support and later turned into a neat optimization with significant code size savings. But it's really just an optimization so there is nothing wrong with just dropping the option (and whatever else goes along with it, I forgot all the nasty details) on the floor if due to a vintage compiler it can't be suported. Signed-off-by:
Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Derived from the i386 variant with a few x86 complexities chopped off. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
This replaces the MIPS-specific to_tm function with the generic rtc_time_to_tm function. The big difference between the two functions is that rtc_time_to_tm uses epoch 70 while to_tm uses 1970, so the result of rtc_time_to_tm needs to be fixed up. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Hard to follow who is pointing what to where and why so it's simply getting in the way of the time code renovation. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ahmed S. Darwish authored
Signed-off-by:
Ahmed S. Darwish <darwish.07@gmail.com> Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
This has not been any serious user of this ill conceived thing since the original invention in like '95. Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle authored
Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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