- 22 Feb, 2024 39 commits
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Victor Lu authored
IH_CHICKEN is blocked for VF writes; this access should be skipped. Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Victor Lu authored
The current error detection only looks for a timeout. This should be changed to also check scratch_reg1 for any errors returned from RLCG. v2: remove new error value Signed-off-by:
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Yifan Zhang authored
This patch to enable MES for GC 11.5.1 Reviewed-by:
shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch to add GC 11.5.1 support Signed-off-by:
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Yifan Zhang authored
Enable KFD for GC 11.5.1. Signed-off-by:
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Tim Huang authored
Enable CGPG support for GFX ip v11.5.1 Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Yifan Zhang authored
Initialize gfx 11.5.0 and set gfx hw configuration. v2: squash in CG, PG, GFXOFF fixes (Alex) Signed-off-by:
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Yifan Zhang authored
This patch to add MES PIPE0 and PIPE1 firmware support for gc_11_5_1. Signed-off-by:
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Yifan Zhang authored
This patch is to add imu firmware support for GC 11.5.1 Signed-off-by:
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Yifan Zhang authored
This patch is to add firmware for GC 11.5.1 Signed-off-by:
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Yifan Zhang authored
This patch to add GC 11.5.1 to GC 11.5.0 family. Signed-off-by:
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Yifan Zhang authored
This patch to enable soc21 support for GC 11.5.1 Signed-off-by:
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Yifan Zhang authored
Disable clock gating and power gating for now. v2: squash in revision fix (Alex) Signed-off-by:
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Yifan Zhang authored
This patch to enable gmc11 for GC 11.5.1 Signed-off-by:
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Aurabindo Pillai authored
Add new firmware header definitions reqiured for DCN401 Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
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Aric Cyr authored
This version brings along the following: - Re-enable windowed MPO support for DCN32/321 - Improvements in the subvp feature - Code clean up - USB4 fixes Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Aric Cyr authored
[Why] Nanosec stats can overflow on long running systems potentially causing statistic logging issues. [How] Use 64bit types for nanosec stats to ensure no overflow. Reviewed-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
A long time ago, the slab header was added to multiple files in DC. We also included it in the os_types.h, which is included in many of those DC files. At this point, there is no need to insert the slab.h header in multiple files, so this commit drops those includes. Tested-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] The feature was disabled due to regression found during testing. Now that all the pending issues are addressed, we are reenabling the power saving feature again. The feature optimizes dispclk level when user is using MPO capable broswers or watching MPO capable videos in windowed mode. The feature achieves power optimization by utilizing free pipes to process incoming pixels in parallel. So it reduces max dispclk requirements for each pipe. Previously ODM power optimization will be disabled when MPO plane is present due to technical challeges. This is mainly because ODM divides pixel workload with respect to stream but MPO plane position and size are arbitrary with respect to stream. The pixel processing workload of an MPO plane is not guarenteed to be evenly distributed across DCN pipes. For example if a plane is moved inside single ODM slice, all the processing for the plane is distributed to the pipe in the current ODM slice, while the other ODM slices don't need to process this plane. If the plane is then moved to the middle crosing two ODM slices, each ODM slice gets half of the workload. This is especially difficult when the plane itself has a large source rect which can't be processed by single DCN pipe. In this case we can't enable ODM power optimization when the plane is only within one ODM slice. [how] To overcome the challeges, new pipe resource management is in place to make sure a plane is validated with ODM power optimization support if it can be validated regardless of its position and the same pipe topology can be used regardless of the plane's position. When the plane is moved outside current ODM slice, we will set recout to 0 so the pipe can be idling without the need to update pipe topology. When the user resizes a plane, it may result in downscaling ratio changes. When the downscaling ratio is above single pipe's threshold, we will seamlessly exit ODM power optimization and applies MPC combine to support the plane. when downscaling ratio becomes smaller, we will seamlessly enter ODM power optimization again. All these pipe transitions happen automatically and quietly when the conditions are met without any visual impacts to the user. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Alvin Lee authored
Subvp bugs related to 8K60 have been fixed, so remove the limit that blocks 8K60 timings from enabling SubVP. Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
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Ethan Bitnun authored
Prevent logs during a prepare_bandwidth call to ensure log accuracy. Reviewed-by:
Ethan Bitnun <etbitnun@amd.com> Signed-off-by:
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Swapnil Patel authored
[Why] Currently there is an error while translating input clock sates into output clock states. The highest fclk setting from output sates is being dropped because of this error. [How] For dcn35 and dcn351, make output_states equal to input states. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Swapnil Patel <swapnil.patel@amd.com> Signed-off-by:
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Alvin Lee authored
Previously the new minimal transition path was only used for windowed MPO + ODM for plane scaling updates. However, we want to generalize the transition for all cases whenever a non-seamless transition is detected (such as for MPO -> SubVP + MPC). To make this change we add pointers in the plane state, stream, and pointers in the stream state to the dc_scratch state and backup and restore these so the minimal transition can take place successfully. Reviewed-by:
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George Shen authored
[Why] Currently, driver state for DCN3.2 is not strictly matching HW state for the USBC port. To reduce inconsistencies while debugging, the driver should match HW configuration. [How] Update link encoder flag to indicate USBC port. Call into DMUB to check when DP Alt mode is entered, and also to check for 2-lane versuse 4-lane mode. Reviewed-by:
George Shen <george.shen@amd.com> Signed-off-by:
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Asad Kamal authored
Remove pcie bw sys entry for asics not supporting such function Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Asad Kamal authored
pcie usage is now handled by fw This reverts commit 8d759dc6. Signed-off-by:
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Srinivasan Shanmugam authored
Fixes potential null pointer dereference warnings in the dc_dmub_srv_cmd_list_queue_execute() and dc_dmub_srv_is_hw_pwr_up() functions. In both functions, the 'dc_dmub_srv' variable was being dereferenced before it was checked for null. This could lead to a null pointer dereference if 'dc_dmub_srv' is null. The fix is to check if 'dc_dmub_srv' is null before dereferencing it. Thus moving the null checks for 'dc_dmub_srv' to the beginning of the functions to ensure that 'dc_dmub_srv' is not null when it is dereferenced. Found by smatch & thus fixing the below: drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:133 dc_dmub_srv_cmd_list_queue_execute() warn: variable dereferenced before check 'dc_dmub_srv' (see line 128) drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:1167 dc_dmub_srv_is_hw_pwr_up() warn: variable dereferenced before check 'dc_dmub_srv' (see line 1164) Fixes: 028bac58 ("drm/amd/display: decouple dmcub execution to reduce lock granularity") Fixes: 65138eb7 ("drm/amd/display: Add DCN35 DMUB") Cc: JinZe.Xu <jinze.xu@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Josip Pavic <josip.pavic@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] VBIOS DMCUB firmware doesn't set the dal_fw bit and we end up hanging waiting for HW power up done because of it. [How] Simplify the path and allow mailbox_rdy to be a functional check when we detect VBIOS firmware. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Lewis Huang authored
[Why] The old asic only have 1 pwrseq hw. We don't need to map the diginst to pwrseq inst in old asic. [How] 1. Only mapping dig to pwrseq for new asic. 2. Move mapping function into dcn specific panel control component Cc: Stable <stable@vger.kernel.org> # v6.6+ Cc: Mario Limonciello <mario.limonciello@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3122Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Lewis Huang <lewis.huang@amd.com> Signed-off-by:
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Ma Jun authored
Drop redundant parameters in function amdgpu_gfx_kiq_init_ring to simplify the code Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Reviewed-by:
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Asad Kamal authored
Remove implementation to get pcie usage for nbio v7.9 as pcie usage is handled by fw This reverts commit 59070fd9. Signed-off-by:
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Wayne Lin authored
[Why] Observe error message "Can't retrieve aconnector in hpd_rx_irq_offload_work" when boot up with a mst tbt4 dock connected. After analyzing, there are few parts needed to be adjusted: 1. hpd_rx_offload_wq[].aconnector is not initialzed before the dmub outbox hpd_irq handler get registered which causes the error message. 2. registeration of hpd and hpd_rx_irq event for usb4 dp tunneling is not aligned with legacy interface sequence [How] Put DMUB_NOTIFICATION_HPD and DMUB_NOTIFICATION_HPD_IRQ handler registration into register_hpd_handlers() to align other interfaces and get hpd_rx_offload_wq[].aconnector initialized earlier than that. Leave DMUB_NOTIFICATION_AUX_REPLY registered as it was since we need that while calling dc_link_detect(). USB4 connection status will be proactively detected by dc_link_detect_connection_type() in amdgpu_dm_initialize_drm_device() Cc: Stable <stable@vger.kernel.org> Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
The function dcn32_build_wm_range_table call DC_FP_START/END. Drop the unnecessary FPU guard. Tested-by:
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Rodrigo Siqueira authored
Instead of only asserting in the case of the SMU wait time is not what we expect, add the SMU timeout check and try again. Tested-by:
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Rodrigo Siqueira authored
The file rv1_clk_mgr_clk.c is not used and for this reason useless. Drop the unnecessary file. Tested-by:
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Rodrigo Siqueira authored
Set a default value for target_div. Tested-by:
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Yifan Zhang authored
Add tmz support for GC 11.5.1. Signed-off-by:
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Hawking Zhang authored
Only do this from host side. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch to add GFXHUB 11.5.1 support. Signed-off-by:
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- 19 Feb, 2024 1 commit
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Yifan Zhang authored
This patch to add MMHUB 3.3.1 support. v2: squash in fault info fix (Alex) Signed-off-by:
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