- 07 Oct, 2014 1 commit
-
-
Benjamin Herrenschmidt authored
When reading from the LPC, the OPAL FW calls return the value via pointer to a uint32_t which is always returned big endian. Our internal inb/outb implementation byteswaps that fine but our debugfs code is still broken. Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: <stable@vger.kernel.org> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
-
- 03 Oct, 2014 6 commits
-
-
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.gitMichael Ellerman authored
Freescale updates from Scott (27 commits): "Highlights include DMA32 zone support (SATA, USB, etc now works on 64-bit FSL kernels), MSI changes, 8xx optimizations and cleanup, t104x board support, and PrPMC PCI enumeration."
-
Michael Ellerman authored
It pulls in more code, including causing us to build a relocatable kernel, which is good for testing. The resulting kernel is still usable as a non-crash dump kernel. Signed-off-by: -
Michael Ellerman authored
For __ioremap(). Signed-off-by: -
Michael Ellerman authored
Because powernv arrived after these other platforms, the defconfigs didn't have PPC_POWERNV disabled, and being default y it gets turned on. If we're going to bother having defconfigs for the specific platforms then they should only build the code required for those platforms. The grab bag of everything config is ppc64_defconfig. Signed-off-by: -
Wei Yang authored
pci_bus_find_capability() is decleared in pci.h, so it is not necessary to do it again. This patch removes it. Signed-off-by:
Wei Yang <weiyang@linux.vnet.ibm.com> Reviewed-by:
Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by:
-
Alexey Kardashevskiy authored
rtas_call() accepts and returns values in CPU endianness. The ddw_query_response and ddw_create_response structs members are defined and treated as BE but as they are passed to rtas_call() as (u32 *) and they get byteswapped automatically, the data is CPU-endian. This fixes ddw_query_response and ddw_create_response definitions and use. of_read_number() is designed to work with device tree cells - it assumes the input is big-endian and returns data in CPU-endian. However due to the ddw_create_response struct fix, create.addr_hi/lo are already CPU-endian so do not byteswap them. ddw_avail is a pointer to the "ibm,ddw-applicable" property which contains 3 cells which are big-endian as it is a device tree. rtas_call() accepts a RTAS token in CPU-endian. This makes use of of_property_read_u32_array to byte swap and avoid the need for a number of be32_to_cpu calls. Cc: stable@vger.kernel.org # v3.13+ Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: folded Anton's patch with of_property_read_u32_array] Signed-off-by:
Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
-
- 02 Oct, 2014 8 commits
-
-
Anton Blanchard authored
Add printk levels to some places in the powerpc port. Signed-off-by:
-
Anton Blanchard authored
Add printk levels to powernv platform code, and convert to pr_err() etc while here. Signed-off-by:
-
Anton Blanchard authored
There is no need for yet another copy of the command line, just use boot_command_line like everyone else. Signed-off-by:
-
Anton Blanchard authored
Use pr_fmt to give some context to the error messages in the module code, and convert open coded debug printk to pr_debug. Use pr_err for error messages. Signed-off-by:
-
Anton Blanchard authored
Fill in the si_addr_lsb siginfo field so the hwpoison code can pass to userspace the length of memory that has been corrupted. Signed-off-by:
-
Anton Blanchard authored
do_page_fault was missing knowledge of HWPOISON, and we would oops if userspace tried to access a poisoned page: kernel BUG at arch/powerpc/mm/fault.c:180! Signed-off-by:
-
Anton Blanchard authored
Exit out early for a kernel fault, avoiding indenting of most of the function. Signed-off-by:
-
Anton Blanchard authored
Unroll clear_page 8 times. A simple microbenchmark which allocates and frees a zeroed page: for (i = 0; i < iterations; i++) { unsigned long p = __get_free_page(GFP_KERNEL | __GFP_ZERO); free_page(p); } improves 20% on POWER8. This assumes cacheline sizes won't grow beyond 512 bytes or page sizes wont drop below 1kB, which is unlikely, but we could add a runtime check during early init if it makes people nervous. Michael found that some versions of gcc produce quite bad code (all multiplies), so we give gcc a hand by using shifts and adds. Signed-off-by:
-
- 01 Oct, 2014 1 commit
-
-
Gavin Shan authored
As Michael suggested, the hex prefix for the output of EEH PE state sysfs entry (/sys/bus/pci/devices/xxx/eeh_pe_state) is always informative to users. Suggested-by:
-
- 30 Sep, 2014 24 commits
-
-
Gavin Shan authored
The dma_get_required_mask() function is used by some drivers to query the platform about what DMA mask is needed to cover all of memory. This is a bit of a strange semantic when we have to choose between IOMMU translation or bypass, but essentially what it means is "what DMA mask will give best performances". Currently, our IOMMU backend always returns a 32-bit mask here, we don't do anything special to it when we have bypass available. This causes some drivers to choose a 32-bit mask, thus losing the ability to use the bypass window, thinking this is more efficient. The problem was reported from the driver of following device: 0004:03:00.0 0107: 1000:0087 (rev 05) 0004:03:00.0 Serial Attached SCSI controller: LSI Logic / Symbios \ Logic SAS2308 PCI-Express Fusion-MPT SAS-2 (rev 05) This patch adds an override of that function in order to, instead, return a 64-bit mask whenever a bypass window is available in order for drivers to prefer this configuration. Reported-by:Murali N. Iyer <mniyer@us.ibm.com> Suggested-by:
-
Gavin Shan authored
It should have been part of commit 1ad7a72c ("powerpc/eeh: Report frozen parent PE prior to child PE"). There are 2 ways to report EEH errors: proactively polling because of 0xFF's returned from PCI config or IO read, or interrupt driven event. We missed to report and handle parent frozen PE prior to child frozen PE for the later case on PowerNV platform. Signed-off-by:
-
Gavin Shan authored
The PEs can be organized as nested. Current implementation doesn't dump PCI config space for subordinate devices of child PEs. However, the frozen PE could be caused by those subordinate devices of its child PEs. The patch dumps PCI config space for all subordinate devices of the problematic PE. Signed-off-by:
-
Gavin Shan authored
When enabling EEH functionality on passed through devices (PE) with VFIO, the devices in the PE would be removed permanently from guest side. In that case, the PE remains frozen state. When returning PE to host, or restarting the guest again, we had mechanism unfreezing the PE by clearing PESTA/B frozen bits. However, that's not enough for some adapters, which are indicated as following "lspci" shows. Those adapters require hot reset on the parent bus to bring their firmware back to workable state. Otherwise, those adaptrs won't be operative and the host (for returning case) or the guest will fail to load the drivers for those adapters without exception. 0000:01:00.0 Ethernet controller: Emulex Corporation OneConnect \ 10Gb NIC (be3) (rev 02) 0000:01:00.0 0200: 19a2:0710 (rev 02) 0001:03:00.0 Ethernet controller: Emulex Corporation OneConnect \ NIC (Lancer) (rev 10) 0001:03:00.0 0200: 10df:e220 (rev 10) The patch adds mechanism to emulate EEH recovery (for hot reset on parent PCI bus) on 3 gates to fix the issue: open/release one adapter of the PE, enable EEH functionality on one adapter of the PE. Reported-by:Murilo Fossa Vicentini <muvic@br.ibm.com> Signed-off-by:
-
Gavin Shan authored
PE would be owned by userland, which probably request PE reset done in host side. During the reset, we should drop the PCI config accesses to the PE with help of flag EEH_PE_RESET. Signed-off-by:
-
Gavin Shan authored
The names of PCI reset scopes aren't sychronized with firmware. The patch fixes it. Signed-off-by:
-
Gavin Shan authored
As Anton suggested, the patch decreases the message level on EEH initialization to avoid unnecessary messages if required. Also, we have unified hint if any of needful RTAS calls is missed, and then we can check /proc/device-tree to figure out the missed RTAS calls. Suggested-by:
-
Gavin Shan authored
Function pcibios_set_pcie_reset_state() can be used to do PCI reset. PCI config access during the reset usually causes EEH errors unexpectedly. In order to avoid the EEH error, the patch blocks PCI config access during reset with the help of flag EEH_PE_RESET, which is similar to what we did in EEH PE reset path. Signed-off-by:
-
Gavin Shan authored
The patch uses eeh_unfreeze_pe() to replace the logic clearing frozen IO and DMA, in order to simplify the code. Signed-off-by:
-
Gavin Shan authored
When passing through PE to guest, that's possibly in frozen state. The driver for the pass-through devices on guest side can't be loaded successfully as reported. We already had one gate in eeh_dev_open() to clear PE frozen state accordingly, but that's not enough because the function is only called at QEMU startup for once. The patch adds another gate in eeh_pe_set_option() so that the PE frozen state can be cleared at QEMU restart time. Signed-off-by:
-
Gavin Shan authored
The function eeh_pci_enable() is called to apply various requests to one particular PE: Enabling EEH, Disabling EEH, Enabling IO, Enabling DMA, Freezing PE. When enabling IO or DMA on one specific PE, we need check that IO or DMA isn't enabled previously. But the condition used to do the check isn't completely correct because one PE would be in DMA frozen state with workable IO path, or vice versa. The patch fixes the improper condition. Signed-off-by:
-
Gavin Shan authored
The problem was reported by Carol: In the scenario of passing mlx4 adapter to guest, EEH error could be recovered successfully. When returning the device back to host, the driver (mlx4_core.ko) couldn't be loaded successfully because of error number -5 (-EIO) returned from mlx4_get_ownership(), which hits offlined PCI device. The root cause is that we missed to put the affected devices into normal state on clearing PE isolated state right after PE reset. The patch fixes above issue by putting the affected devices to normal state when clearing PE isolated state in eeh_pe_state_clear(). Cc: stable@vger.kernel.org Reported-by:
Carol L. Soto <clsoto@us.ibm.com> Signed-off-by:
-
Gavin Shan authored
The frozen state on one specific PE is probably caused by error injection, which is done with help of PAPR error injection registers. According to the hardware spec, those registers should be cleared automatically after one-shot frozen PE. However, that's not always true, at least on P7IOC of Firebird-L. So we have to clear them before doing PE reset to avoid recursive EEH errors at recovery stage. Signed-off-by:
-
Mike Qiu authored
The patch adds debugfs file (/sys/kernel/debug/powerpc/PCIxxxx/ err_injct), which accepts following formated string, to support error injection. It will be used to support userland utility "errinjct" in future. "pe_no:0:function:address:mask" - 32-bits PCI errors "pe_no:1:function:address:mask" - 64-bits PCI errors Signed-off-by:
Mike Qiu <qiudayu@linux.vnet.ibm.com> Signed-off-by:
-
Gavin Shan authored
The patch introduces eeh_ops::err_inject(), which allows to inject specified errors to indicated PE for testing purpose. The functionality isn't support on pSeries platform. On PowerNV, the functionality relies on OPAL API opal_pci_err_inject(). Signed-off-by:
-
Gavin Shan authored
The patch synchronizes firmware header file (opal.h) for PCI error injection. Signed-off-by:
-
Gavin Shan authored
When passing through device, its PE might have been put into frozen state. One obvious example would be: the passed PE is forced to be offline because of hitting maximal allowed EEH errors in userland. In that case, the frozen state won't be cleared and then the PE is returned back to host, which might not have chance detecting and recovering from it. The patch adds more check when passing through device and clear the PE frozen state if necessary. Signed-off-by:
-
Gavin Shan authored
The PCI devices that have been passed through are enabled before reset, we need restore to the enabled state after reset. Otherwise, MMIO access might be issued to disabled devices after reset and causes exceptional recursive EEH error. Signed-off-by:
-
Gavin Shan authored
The patch adds one more option (EEH_OPT_FREEZE_PE) to set_option() method to proactively freeze PE, which will be issued before resetting pass-throughed PE to drop MMIO access during reset because it's always contributing to recursive EEH error. Signed-off-by:
-
Gavin Shan authored
The patch adds sysfs entry "eeh_pe_state". Reading on it returns the PE's state while writing to it clears the frozen state. It's used to check or clear the PE frozen state from userland for debugging purpose. The patch also replaces printk(KERN_WARNING ...) with pr_warn() in eeh_sysfs.c Signed-off-by:
-
Gavin Shan authored
eeh_check_failure() is used to check frozen state of the PE which owns the indicated I/O address. The argument "val" of the function isn't used. The patch drops it and return the frozen state of the PE as expected. Cc: Vishal Mansur <vmansur@linux.vnet.ibm.com> Signed-off-by:
-
Anton Blanchard authored
Enable on DCACHE_WORD_ACCESS on ppc64le. It should work on ppc64 and ppc32 but we need to do some testing first. A somewhat reasonable testcase used to show the performance improvement - a repeated stat of a 33 byte filename that doesn't exist: #include <sys/types.h> #include <sys/stat.h> #include <unistd.h> #define ITERATIONS 10000000 #define PATH "123456781234567812345678123456781" int main(void) { unsigned long i; struct stat buf; for (i = 0; i < ITERATIONS; i++) stat(PATH, &buf); return 0; } runs 27% faster on POWER8. Signed-off-by: -
Anton Blanchard authored
Use cmpb which compares each byte in two 64 bit values and for each matching byte places 0xff in the target and 0x00 otherwise. A simple hash_name microbenchmark: http://ozlabs.org/~anton/junkcode/hash_name_bench.c shows this version to be 10-20% faster than running the x86 version on POWER8, depending on the length. Signed-off-by:
-
Michael Ellerman authored
It is a rarely exercised case, so we want to have a test to ensure it works as required. Signed-off-by:
-
