- 08 Dec, 2023 22 commits
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Rajendra Nayak authored
Oryon is the custom ARM CPU core implementation used in Qualcomm's X1E80100 SoC, document it. Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by:
Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
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Bjorn Andersson authored
Merge branch 'icc-x1e80100' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 Merge the X1E80100 interconnect binding to get access to the interconnect port constants.
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Bjorn Andersson authored
Merge the X1E80100 clock bindings to get access to the clock constants.
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Rajendra Nayak authored
Add bindings and update documentation for clock rpmh driver on X1E80100 SoCs. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-4-quic_sibis@quicinc.comSigned-off-by:
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Rajendra Nayak authored
Add device tree bindings for global clock controller on X1E80100 SoCs. Signed-off-by:
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Krzysztof Kozlowski authored
Add nodes for WSA8845 speakers on SM8650 MTP board. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add nodes for LPASS Soundwire v2.0.0 controllers. Use labels with indices matching downstream DTS, to make any comparisons easier. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8650. The nodes are very similar to SM8550. Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin controller device node as part of audio subsystem in Qualcomm SM8650 SoC. Cc: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
Add the ADSP Generic Packet Router (GPR) device node as part of audio subsystem in Qualcomm SM8650 SoC. Cc: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Neil Armstrong authored
Enable IPA on the SM8650 QRD. The GSI firmware on this platform is loaded by the AP. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231201-topic-sm8650-upstream-ipa-v1-2-7e8cf7200cd2@linaro.orgSigned-off-by:
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Neil Armstrong authored
Add IPA-related nodes and definitions to SM8650 dtsi, which uses IPA v5.5.1 a minor revision of v5.5 found in the SM8550 SoC. Signed-off-by:
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Neil Armstrong authored
Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 QRD board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink - Bluetooth Reviewed-by:
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Neil Armstrong authored
Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 MTP board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink Reviewed-by:
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Neil Armstrong authored
Add Hardware nodes that depends on an interconnect property to be valid. The includes: - all QUP i2s/spi nodes - PCIe - UFS - SDHCI - Display - HWMON Acked-by:
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Neil Armstrong authored
Add initial QRD (Qualcomm Reference Device) DT, it supports boot to shell with buttons, leds and USB peripheral. Reviewed-by:
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Neil Armstrong authored
Add initial QRD (Qualcomm Reference Device) DT, only boots to shell with USB device support. Reviewed-by:
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Neil Armstrong authored
The pm8550ve can be found with a different SID on SM8650 platforms, make it configurable. Reviewed-by:
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Neil Armstrong authored
Add initial DTSI for the Qualcomm SM8650 platform, only contains nodes which doesn't depend on interconnect. Reviewed-by:
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Neil Armstrong authored
Document the SM8650 SoC and based MTP (Mobile Test Platforms) and QRD (Qualcomm Reference Device) boards. Reviewed-by:
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Bjorn Andersson authored
Merge branch 'icc-sm8650' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 Merge the SM8650 interconnect binding, to gain access to the interconnect port constants.
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Bjorn Andersson authored
Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into arm64-for-6.8 Merge the SM8650 clock bindings, to gain access to the clock constants.
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- 07 Dec, 2023 18 commits
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Luka Panio authored
Initial support for Xiaomi Pad 6 tablet, that have sm8250 soc. Signed-off-by:
Luka Panio <lukapanio@gmail.com> Acked-by:
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Luka Panio authored
Add a compatible for Xiaomi Pad 6. Acked-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Alex Elder authored
Enable IPA on the SM8550 QRD. The GSI firmware on this platform is loaded by the AP. Signed-off-by:
Alex Elder <elder@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Link: https://lore.kernel.org/r/20231124181718.915208-3-elder@linaro.orgSigned-off-by:
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Alex Elder authored
Add IPA-related nodes and definitions to "sm8550.dtsi", which uses IPA v5.5. Signed-off-by:
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Sibi Sankar authored
Extend pattern matching to support the X1E platform name. Signed-off-by:
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by:
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Robert Marko authored
Add node to support the QUP4 SPI controller inside of IPQ8074. Some devices use this bus to communicate to a Bluetooth controller. Signed-off-by:
Robert Marko <robimarko@gmail.com> Link: https://lore.kernel.org/r/20231123121324.1046164-1-robimarko@gmail.comSigned-off-by:
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Imran Shaik authored
Add device node for ECPRI clock controller on qcom QDU1000 and QRU1000 SoCs. Signed-off-by:
Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Note that only triggering on rising edges can be used to detect resume events but not disconnect events. Fixes: 7f7e5c1b ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Reviewed-by:
Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231120164331.8116-12-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: 0c9dde0d ("arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes") Fixes: b33d2868 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes") Cc: stable@vger.kernel.org # 5.10 Cc: Jonathan Marek <jonathan@marek.ca> Cc: Jack Pham <quic_jackp@quicinc.com> Signed-off-by:
Jack Pham <quic_jackp@quicinc.com> Link: https://lore.kernel.org/r/20231120164331.8116-11-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: 59d34ca9 ("arm64: dts: qcom: Add initial device tree for SM6375") Cc: stable@vger.kernel.org # 6.2 Cc: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: ca4db2b5 ("arm64: dts: qcom: sdm845: Add USB-related nodes") Cc: stable@vger.kernel.org # 4.20 Signed-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: 07c8ded6 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees") Cc: stable@vger.kernel.org # 6.2 Cc: Richard Acayan <mailingradian@gmail.com> Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20231120164331.8116-8-johan+linaro@kernel.orgSigned-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: b080f53a ("arm64: dts: qcom: sc8180x: Add remoteprocs, wifi and usb nodes") Cc: stable@vger.kernel.org # 6.5 Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Note that only triggering on rising edges can be used to detect resume events but not disconnect events. Fixes: bb9efa59 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by:
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Johan Hovold authored
A recent cleanup reordering the usb_1 wakeup interrupts inadvertently switched the DP and SuperSpeed interrupt trigger types. Fixes: 4a7ffc10 ("arm64: dts: qcom: align DWC3 USB interrupts with DT schema") Cc: stable@vger.kernel.org # 5.19 Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Fixes: 0b766e7f ("arm64: dts: qcom: sc7180: Add USB related nodes") Cc: stable@vger.kernel.org # 5.10 Signed-off-by:
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Johan Hovold authored
The DP/DM wakeup interrupts are edge triggered and which edge to trigger on depends on use-case and whether a Low speed or Full/High speed device is connected. Note that only triggering on rising edges can be used to detect resume events but not disconnect events. Fixes: de100152 ("arm64: dts: qcom: sa8775p: add USB nodes") Cc: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20231120164331.8116-3-johan+linaro@kernel.orgSigned-off-by:
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