- 30 Mar, 2017 40 commits
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Junwei Zhang authored
This handles nbio 6.1 specific implementations which are used by various other IPs. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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Alex Xie authored
Reviewed-by:
Alex Xie <AlexBin.Xie@amd.com> Signed-off-by:
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Alex Xie authored
Reviewed-by:
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Alex Deucher authored
Flags need to be 0 to be considered invalid. Reviewed-by:
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Huang Rui authored
Defines the header info for the psp firmware. Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Huang Rui authored
Handle ucode differences in vega10. Acked-by:
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Marek Olšák authored
Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
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Alex Deucher authored
v2: Marek: allow shifts >32 in AMDGPU_TILING_SET/GET Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
NGG (Next Generation Graphics) is a new feature in GFX9.0. This adds the relevant parameters. Acked-by:
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Alex Deucher authored
New on SOC-15 asics. Signed-off-by: -
Christian König authored
This allows us to grab IVs without spamming the log. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Alex Deucher authored
Reflect the new format on soc-15 asics. Reviewed-by:
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Alex Deucher authored
If the board is atomfirmware based. Acked-by:
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Alex Xie authored
Signed-off-by:
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Ken Wang authored
Signed-off-by:
Ken Wang <Qingqing.Wang@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Acked-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
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Huang Rui authored
This patch introduces a new flag named "amdgpu_firmware_load_type" to handle different firmware loading method. Since Vega10, there are three ways to load firmware. It would be better to use a flag and a fw_load_type kernel parameter to configure it. Acked-by:
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ken authored
Signed-off-by:
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Ken Wang authored
Acked-by:
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Ken Wang authored
These are used by various IP modules. Acked-by:
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Alex Deucher authored
Acked-by:
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Alex Deucher authored
Acked-by:
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Felix Kuehling authored
This header defines the gfx v9 MEC structures. Acked-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by:
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Alex Deucher authored
These are the Video Compression Engine registers for vega10. Signed-off-by: -
Alex Deucher authored
These are the Unifed Video Decoder registers for vega10. Signed-off-by: -
Alex Deucher authored
These are the THerMal control registers for vega10. Signed-off-by: -
Alex Deucher authored
These are the System Managment Unit IO registers for vega10. Signed-off-by: -
Alex Deucher authored
These are the System DMA register headers for vega10. Signed-off-by: -
Alex Deucher authored
These are the OS Services register headers for vega10. Signed-off-by: -
Alex Deucher authored
These are the Bus IO registers for vega10. Signed-off-by: -
Alex Deucher authored
These are the Bus InterFace registers for vega10. Signed-off-by: -
Alex Deucher authored
MP is the system management controller on vega10. Signed-off-by: -
Alex Deucher authored
Add the MultiMedia Hub registers for vega10. Signed-off-by: -
Alex Deucher authored
These are the Host Data Path registers for vega10. Signed-off-by: -
Alex Deucher authored
Add the Graphics Core register headers for vega10. Signed-off-by: -
Alex Deucher authored
These are the register headers for the Display and Composition Engine on vega10. Signed-off-by: -
Alex Deucher authored
ATHUB is part of the memory controller on soc15 asics. Signed-off-by: -
Alex Deucher authored
This adds the register bitfield enums for vega10. Signed-off-by: -
Alex Deucher authored
This header defines the IP layout for soc15 based SoCs. Signed-off-by:
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