- 05 Mar, 2018 36 commits
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Christian König authored
Those belong to the TTM handling. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
There have been many reports of Ellesmere and Baffin systems not being able to drive HDMI 4k60 due to the fact that we check the HDMI_6GB_EN bit from VBIOS table. Windows seems to not have this issue. On some systems we fail to the encoder cap info from VBIOS. In that case we should default to enabling HDMI6G support. This was tested by dwagner on https://bugs.freedesktop.org/show_bug.cgi?id=102820Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Shirish S authored
This patch updates the dc's plane state with the parameters set by the user side. This is needed to validate the plane capabilities with the parameters user space wants to set. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Harry Wentland authored
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Shirish S authored
CZ & ST support uptil a limit 2:1 downscaling, this patch adds validate_plane hook, that shall be used to validate the plane attributes sent by the user space based on dce110 capabilities. Signed-off-by:
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Shirish S authored
amdgpu_dm_atomic_check() is used to validate the entire configuration of planes and crtc's that the user space wants to commit. However amdgpu_dm_atomic_check() depends upon DRM_MODE_ATOMIC_ALLOW_MODESET flag else its mostly dummy. Its not mandatory for the user space to set DRM_MODE_ATOMIC_ALLOW_MODESET, and in general its not set either along with DRM_MODE_ATOMIC_TEST_ONLY. Considering its importantance, this patch defers the allow_modeset check in dm_update_planes_state(), so that there shall be scope to validate the configuration sent from user space, without impacting the population of dc/dm related data structures. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Tony Cheng authored
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Harry Wentland authored
This is really just a copy of dm_pp_clocks_state, so just use that one. Thanks to Matthias Kaehlke for spotting this. Signed-off-by:
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Eric Yang authored
Before dig fe is enabled, infoframe can't be programmed. So in suspend resume case our infoframe programmming was not going through. This change changes the sequence so that infoframe is programmed after. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Applying min dispclk patch would result in incorrect dppclk divider without this change Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Created a DC_LOGGER define. This is used to pass the logger into the macros. Anywhere we need to use the logger we need to define DC_LOGGER Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Created MACROS for all log levels. Also Replaced usage of dm_logger_write to the defined MACROS Signed-off-by:
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Vitaly Prosyak authored
Implementation of de-gamma, blnd-gamma, shaper and 3d lut's. Removed memory allocations in transfer functions. Refactor color module. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Tony Cheng authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
v2: Fix commit title Signed-off-by:
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Dmytro Laktyushkin authored
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Shirish S authored
Currently the FBC buffer is allocated in VRAM, since VRAM usage is dedicatedly for scanouts, by allocating FBC back buffer in GTT shall help in conserving VRAM for other purposes. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Leo (Sunpeng) Li authored
Mask and shift values for DCP0_REGAMMA_LUT_WRITE_EN_MASK were missing from XFM_COMMON_MASK_SH_LIST_SOC_BASE. Add it. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Wenjing Liu authored
[Description] When CR fails to minimum link rate, we should reduce lane count to the number lowest cr_done lanes. [Code Review] Jun Lei Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Xingyue Tao authored
Brightness could not be changed for some panels whose DPCD_version is below 1.2 Now psr_version is added into stream, and it copies from the displayTarget's psr_version. It checks if the stream's psr_versio is non-zero and sets the vsc info packet revision now. Signed-off-by:
Xingyue Tao <xingyue.tao@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
This patch fixed secondary screen only S4 resume, eDP is unintentionally light up due to incorrect dpms off flag. When entering S4, dpms off flags are set to true via set power state. During resume, eDP is light up by vbios, so the flags should be changed to false to match the real state. By change the flag properly, eDP is able to be turned off properly as per OS request. This change may affect S3/S4 Shut down resume IOIC, need to verify those cases. Signed-off-by:
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Eric Yang authored
Optimization in reset backend skips disable stream if it is already done in dc_stream_set_dpms. However that path does not disable az in order to prevent audio from toggling between internal and external displays. This still need to be done. Signed-off-by:
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Tony Cheng authored
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Hersen Wu authored
[Description] ASIC change debug register definition Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
Points in the DRM LUT are spaced linearly. Points in hardware are spaced exponentially, with greater density towards 0. To maintain low-end accuracy in hardware when sampling the DRM LUT, more points are needed. However, X doesn't seem to play with legacy LUTs of such size. Therefore, check for legacy lut when updating DC states, and update accordingly. v2: Use a macro for the maximum drm LUT value. v3: Update commit to reflect that this does not map 1-1 to HW Signed-off-by:
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John Barberiz authored
Add HPD delay timer support to 1. Single/dual link DVI. 2. DP to HDMI passive dongle 3. DP to DVI passive dongle. Signed-off-by:
John Barberiz <jbarberi@amd.com> Reviewed-by:
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Roman Li authored
Clean fake sink flag after detecting link on downstream port. Fixing display light-up after "hot-unplug&plug again" downstream of an active dongle. Signed-off-by:
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Hersen Wu authored
some MST capable scaler doesn't like recieving CLEAR_PAYLOAD_ID_TABLE after link training. move branch initialize to before link training Signed-off-by:
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Matthias Kaehlcke authored
The util mkregtable includes a copy of the kernel API for linked lists, only a small subset of it is used. Delete the unused functions and macros. Reviewed-by:
Guenter Roeck <groeck@chromium.org> Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
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Alex Deucher authored
Rather than querying it every time we need it. Also fixes a crash in VM pass through if there is no root bridge because the cached value fetch already checks this properly. v2: fix includes Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244Acked-by:
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- 01 Mar, 2018 4 commits
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Tom St Denis authored
The read/write pointers on sdma4 devices increment beyond the ring size and should be masked. Tested on my Ryzen 2400G. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Monk Liu authored
sometimes GPU is switched to other VFs and won't swich back soon, so the kiq reg access will not signal within a short period, instead of busy waiting a long time(MAX_KEQ_REG_WAIT) and returning TMO we can istead sleep 5ms and try again later (non irq context) And since the waiting in kiq_r/weg is busy wait, so MAX_KIQ_REG_WAIT shouldn't set to a long time, set it to 10ms is more appropriate. if gpu already in reset state, don't retry the KIQ reg access otherwise it would always hang because KIQ was already die usually. v2: replace schedule() with msleep() for the wait v3: use while loop for the wait repeating use macros for the sleep period more description for it v4: drop unused variable Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com Reviewed-by:
Pixel Ding <Pixel.Ding@amd.com> Signed-off-by:
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Monk Liu authored
1)create a routine "handle_vram_lost" to do the vram recovery, and put it into amdgpu_device_reset/reset_sriov, this way no need of the extra paramter to hold the VRAM LOST information and the related macros can be removed. 3)show vram_recover failure if time out, and set TMO equal to lockup_timeout if vram_recover is under SRIOV runtime mode. 4)report error if any ip reset failed for SR-IOV Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Monk Liu authored
found recover_vram_from_shadow sometimes get executed in paralle with SDMA scheduler, should stop all schedulers before doing gpu reset/recover Signed-off-by:
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