- 17 Feb, 2011 30 commits
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Roman Tereshonkov authored
The current multiblock erase verify read timeout 100us is the maximum for none-error case. If errors happen during multibock erase then the specification recommends to run multiblock erase verify command with maximum timeout 10ms (see specs. for KFM4G16Q2A and KFN8G16Q2A). For the most common non-error case we wait 100us in udelay polling loop. In case of timeout the interrupt mode is used to wait for the command end. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Adrian Hunter authored
OneNAND version ID may not give the highest frequency supported and some OneNAND's have setup times that are clock dependent. Let the board provide that information. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Adrian Hunter authored
OneNAND frequency is determined when calculating GPMC timings. Return that value instead of determining it again in the OMAP OneNAND driver. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Adrian Hunter authored
104MHz needs a latency of 8 clock cycles and the VHF flag must be set. Also t_rdyo is specified as "not applicable" so pick a lower value, and force at least 1 clk between AVD High to OE Low. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Sukumar Ghorai authored
This patch overrides nand ecc layout and bad block descriptor (for 8-bit device) to support hw ecc in romcode layout. So as to have in sync with ecc layout throughout; i.e. x-loader, u-boot and kernel. This enables to flash x-loader, u-boot, kernel, FS images from kernel itself and compatiable with other tools. This patch does not enables this feature by default and need to pass from board file to enable for any board. Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Sukumar Ghorai authored
This patch makes it possible to select sw or hw (different layout options) ecc scheme supported by omap nand driver. Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Sukumar Ghorai authored
Configure the FIFO THREASHOLD value different for read and write to keep busy both filling and to drain out of FIFO at reading and writing. Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Sukumar Ghorai authored
This patch enable prefetch-irq mode for nand transfer(read, write) Signed-off-by: Vimal Singh <vimalsingh@ti.com> Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Sukumar Ghorai authored
add support the irq mode in GPMC. gpmc_init() function move after omap_init_irq() as it has dependecy on irq. Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Sukumar Ghorai authored
nand transfer type (sDMA, Polled, prefetch) can be select from board file, enabling all transfer type in driver, by default. this helps in multi-omap build and to select different transfer type for different board. Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Sukumar Ghorai authored
zoom3 and 3630-sdp having the x16 nand device. This patch configure gpmc as x16 and select the currect function in driver for polled mode (without prefetch enable) transfer. Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
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Govindraj.R authored
McSPI runtime conversion. Changes involves: 1) remove clock framework apis to use runtime framework apis. 2) context restore from runtime resume which is a callback for get_sync. 3) Remove SYSCONFIG(sysc) register handling (a) Remove context save and restore of sysc reg and remove soft reset done from sysc reg as this will be done with hwmod framework. (b) Also cleanup sysc reg bit macros. 4) Rename the omap2_mcspi_reset function to omap2_mcspi_master_setup function as with hwmod changes soft reset will be done in hwmod framework itself and use the return value from clock enable function to return for failure scenarios. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Partha Basak <p-basak2@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Charulatha V authored
Cleans up all base address definitions for omap_mcspi and adapts the device registration and driver to hwmod framework. Changes involves: 1) Removing all base address macro defines. 2) Using omap-device layer to register device and utilizing data from hwmod data file for base address, dma channel number, Irq_number, device attribute(number of chipselect). 3) Appending base address with pdata reg_offset for omap4 boards. For omap4 all regs used in driver deviate with reg_offset_macros defined with an value of 0x100. So pass this offset through pdata and append the same to base address retrieved from hwmod data file and we are not mapping *_HL_* regs which are not used in driver. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Partha Basak <p-basak2@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Charulatha V authored
Update omap3 hwmod data file with McSPI info. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Charulatha V authored
Update the 2430 hwmod data file with McSPI info. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Charulatha V authored
Update the omap2420 hwmod data with the McSPI info. Add a device attribute structure which will be used for passing number of chipselects from hwmod data. Add revision macros to be passed from rev field from hwmod. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Simon Que authored
Build and register an hwspinlock platform device. Although only OMAP4 supports the hardware spinlock module (for now), it is still safe to run this initcall on all omaps, because hwmod lookup will simply fail on hwspinlock-less platforms. Signed-off-by: Simon Que <sque@ti.com> Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Simon Que authored
Add hwspinlock support for the OMAP4 Hardware Spinlock device. The Hardware Spinlock device on OMAP4 provides hardware assistance for synchronization between the multiple processors in the system (dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP). [ohad@wizery.com: adapt to hwspinlock framework, tidy up] Signed-off-by: Simon Que <sque@ti.com> Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Signed-off-by: Krishnamoorthy, Balaji T <balajitk@ti.com> Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Paul Walmsley <paul@pwsan.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Ohad Ben-Cohen authored
Add a platform-independent hwspinlock framework. Hardware spinlock devices are needed, e.g., in order to access data that is shared between remote processors, that otherwise have no alternative mechanism to accomplish synchronization and mutual exclusion operations. Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Hari Kanigeri <h-kanigeri2@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Paul Walmsley <paul@pwsan.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Benoit Cousson authored
OMAP4 hwmod data structures are populated with base address, L3 and L4 interface clocks, IRQs and sysconfig register details. As per OMAP USBOTG specification, need to configure the USBOTG to smart idle/standby or no idle/standby during data transfer and force idle/standby when not in use to support retention and offmode. By setting HWMOD_SWSUP_SIDLE and HWMOD_SWSUP_MSTANDBY flags,framework will take care of configuring to no idle/standby when module is enabled and force idle/standby when idled. Signed-off-by: Cousson, Benoit <b-cousson@ti.com> Signed-off-by: Hema HK <hemahk@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Felipe Balbi <balbi@ti.com> [b-cousson@ti.com: Fix position, opt_clk, and author]
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Benoit Cousson authored
Add more hwmod structures but keep them commented out for the moment until the driver adaptation to hwmod / omap_device is done. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com>
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Benoit Cousson authored
Add mcbsp data including a revision member in hwmod_class in order to provide mcbsp revision information in different omap. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Charulatha V <charu@ti.com> [b-cousson@ti.com: Remove the mcbsp4 memory name, re-order properly the structures]
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Benoit Cousson authored
Add HWMOD entries for the OMAP DMIC. The HWMOD entires define the system resource requirements for the driver such as DMA addresses, channels, and IRQ's. Placing this information in the HWMOD database allows for more generic drivers to be written and having the specific implementation details defined in HWMOD. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: David Lambert <dlambert@ti.com> [b-cousson@ti.com: Change the wrong hwmod name, add missing flag and re-order structures]
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Benoit Cousson authored
Mailbox hwmod data for omap4. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com> [b-cousson@ti.com: Re-order the structures and remove the irq line name]
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Benoit Cousson authored
Add dss, dispc, dsi1, dsi2, hdmi, rfbi and venc hwmods. In OMAP4 there are severals IPs that can be reached by differents interconnect paths depending of the access initiator (MPU vs. SDMA). In the case of the DSS, both L3 direct path and L4 CFG path can be used to access all the DSS IPs. The two ocp_ip already exists to support the two address spaces. +------------+-- L3_MAIN --+ MPU IP | | +-- L4_CFG --+ L3 main address range is specified first, since it is used by default. dss is also considered as an IP as dispc, rfbi, and named as dss_core. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Mayuresh Janorkar <mayur@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com> Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> [b-cousson@ti.com: Re-organize structures to match file convention and remove irq entry from dss_hwmod]
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Benoit Cousson authored
Add the data for the 11 timers IPs. OMAP4 contains two differents IP variants for the timers: - 8 x regular timer (3, 4, 5, 6, 7, 8, 9 & 11) - 3 x 1ms timer (1, 2 & 10) The regular timers registers programming model was changed due to the adaptation to the new IP interface. Unfortunately the 1ms version still use the previous programming model. The driver will have to take care of theses differences. Please note that the capability and the partitioning is also different depending of the instance. - timer 1 is inside the wakeup domain - timers 5, 6, 7 & 8 are inside in the ABE (audio backend) - timers 2, 3, 4, 9, 10 & 11 are inside the PER power domain The timer was previously named gptimerX or dmtimerX, it is now simply named timerX. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> [b-cousson@ti.com: Fix alignement in class attribute, re-order flags and update the changelog]
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Benoit Cousson authored
Update omap4 hwmod file with McSPI info. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Kevin Hilman <khilman@ti.com>
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Benoit Cousson authored
Add hwspinlock hwmod data for OMAP4 chip Signed-off-by: Cousson, Benoit <b-cousson@ti.com> Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Cc: Paul Walmsley <paul@pwsan.com> [b-cousson@ti.com: Move the data to keep the original order and add missing SIDLE_SMART_WKUP flag]
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- 16 Feb, 2011 8 commits
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Tony Lindgren authored
Merge branches 'devel-cleanup', 'devel-board', 'devel-early-init' and 'devel-ti816x' into omap-for-linus
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Tony Lindgren authored
Update to use init_early Signed-off-by: Tony Lindgren <tony@atomide.com>
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Hemant Pedanekar authored
This patch adds support for low level debugging on TI816X boards. Currently the support for UART3 console on TI816X EVM is added. Signed-off-by: Hemant Pedanekar <hemantp@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Hemant Pedanekar authored
This patch adds minimal support and build configuration for TI816X EVM. Signed-off-by: Hemant Pedanekar <hemantp@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Hemant Pedanekar authored
This patch updates the common machine specific source files with support for TI816X. Signed-off-by: Hemant Pedanekar <hemantp@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Hemant Pedanekar authored
This patch updates the common platform files with TI816X support. The approach taken in this patch is to add TI816X as part of OMAP3 variant where the cpu class is considered as OMAP34XX and the type is TI816X. This means, both cpu_is_omap34xx() and cpu_is_ti816x() checks return success on TI816X. A kernel config option CONFIG_SOC_OMAPTI816X is added under OMAP3 to include support for TI816X build. Signed-off-by: Hemant Pedanekar <hemantp@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommuLinus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: m68knommu: set flow handler for secondary interrupt controller of 5249 m68knommu: remove use of IRQ_FLG_LOCK from 68360 platform support m68knommu: fix dereference of port.tty m68knommu: add missing linker __modver section m68knommu: fix mis-named variable int set_irq_chip loop m68knommu: add optimize memmove() function m68k: remove arch specific non-optimized memcmp() m68knommu: fix use of un-defined _TIF_WORK_MASK m68knommu: Rename m548x_wdt.c to m54xx_wdt.c m68knommu: fix m548x_wdt.c compilation after headers renaming m68knommu: Remove dependencies on nonexistent M68KNOMMU
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- 15 Feb, 2011 2 commits
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Greg Ungerer authored
The secondary interrupt controller of the ColdFire 5249 code is not setting the edge triggered flow handler. Set it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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Greg Ungerer authored
The m68knommu arch does not define or use IRQ_FLG_LOCK in its irq subsystem. Remove obsolete use of it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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