- 29 May, 2014 11 commits
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Stephen Boyd authored
A new PLL (gpll4) is added on msm8974 PRO devices to support a faster sdc1 clock rate. Add support for this and the two new sdcc cal clocks. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Stephen Boyd authored
The display clocks all source from dedicated phy PLLs within their respective multimedia hardware block. Hook up these PLLs to the display clocks with the appropriate parent mappings, clock flags, and the appropriate clock ops. This should allow the display clocks to work once the appropriate phy PLL driver registers their PLL clocks. Signed-off-by:
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Stephen Boyd authored
Add support for the DSI/EDP/HDMI RCG clocks. With the proper display driver in place this should allow us to support display clocks on msm8974 based devices. Signed-off-by:
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Stephen Boyd authored
Some drivers may want to call clk_set_rate() with a very large number to force the clock to go as fast as it possibly can without having to know the range between the highest rate and second highest rate. Add support for this by defaulting to the highest rate in the frequency table if we can't find a frequency greater than what is requested. Signed-off-by:
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Stephen Boyd authored
We forgot to add the status bit for the PLLs and we were using the wrong register and masks for configuration, leading to unexpected PLL configurations. Fix this. Fixes: d8b21201 (clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)) Signed-off-by:
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Stephen Boyd authored
If the bit is set the clock is off so we should be checking for a clear bit, not a set bit. Invert the logic. Fixes: bcd61c0f (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by:
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Alexandre Belloni authored
This driver deals with the core clocks found on Marvell Berlin BG2Q. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
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Sebastian Hesselbarth authored
This driver deals with the core clocks found on Marvell Berlin BG2 and BG2CD. For the shared register dividers, make use of the corresponding driver and add some single clock muxes and gates for the rest. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
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Alexandre Belloni authored
This is a driver for the complex divider cells found on Marvell Berlin2 SoCs. The cells come in two flavors: single register cells and shared register cells. Signed-off-by:
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Alexandre Belloni authored
This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by:
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Sebastian Hesselbarth authored
This is a driver for the AVPLLs built upon a VCO with 8 channels each found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share the same register set, sometimes registers shifts for one of the VCOs are a bit off. Nothing serious that should require a separate driver, so deal with both VCOs in a single driver instead. Signed-off-by:
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- 28 May, 2014 9 commits
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Stephen Boyd authored
Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com> Signed-off-by:
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Sachin Kamat authored
Fixes the following warning: WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown) The function exynos4_clk_sleep_init() references the (unknown reference) __initdata (unknown). This is often because exynos4_clk_sleep_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Reported-by:
kbuild test robot <fengguang.wu@intel.com> Signed-off-by:
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Mike Turquette authored
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Mike Turquette authored
Merge tag 'clk-tegra-fixes-3.15' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes PLLE fixes for 3.15
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Simon Horman authored
Add macros usable by device tree sources to reference r8a7779 clocks by index. Based on work for the r8a7791 SoC by Laurent Pinchart. Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Tomasz Figa authored
Commit c686078 ("clk: divider: Add round to closest divider") introduced a helper function to check whether given divisor is the best one instead of direct check. However due to int type used instead of unsigned long for passing calculated rates to this function in certain cases an overflow could occur, for example when trying to obtain maximum possible clock rate by calling clk_round_rate(..., UINT_MAX). This patch fixes this issue by changing the type of rate, now and best arguments of the function to unsigned long, which is the type that should be used for clock rates. Signed-off-by:Tomasz Figa <t.figa@samsung.com> Acked-by:
Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
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Stephen Boyd authored
Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Boris BREZILLON authored
Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Alex Elder authored
Implement the clk->determine_rate method for Broadcom Kona peripheral clocks. This allows a peripheral clock to be re-parented in order to satisfy a rate change request. This takes the place of the previous kona_peri_clk_round_rate() functionality, though that function remains because it is used by the new one. The parent clock that allows the peripheral clock to produce a rate closest to the one requested is the one selected, though the current parent is used by default. Signed-off-by:
Alex Elder <elder@linaro.org> Signed-off-by:
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- 23 May, 2014 17 commits
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Georgi Djakov authored
The address of the blsp2_ahb_clk register is incorrect. Fix it. Signed-off-by:
Georgi Djakov <gdjakov@mm-sol.com> Reviewed-by:
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Krzysztof Kozlowski authored
This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the s2mps11 clock driver. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by:
Yadwinder Singh Brar <yadi.brar@samsung.com> Reviewed-by:
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Krzysztof Kozlowski authored
There is no need for checking if 'clk_table' is not NULL twice (first after allocation and second at the end of probe()). Also move allocation of this 'clk_table' to probe from s2mps11_clk_parse_dt as this is logical place for it. Signed-off-by:
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Krzysztof Kozlowski authored
Add of_clk_del_provider to remove previously registered clock provider. Add of_node_put to decrement the ref count of clock nodes. Signed-off-by:
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Valentin Ilie authored
When it fails to allocate div, gate should be free'd before return Signed-off-by:
Valentin Ilie <valentin.ilie@gmail.com> Signed-off-by:
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Mike Turquette authored
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Mike Turquette authored
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Maxime COQUELIN authored
Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and table dividers") introduces a regression in its _table_round_up function. When the divider passed to this function is greater than the max divider available in the table, this function returns table's max divider. Problem is that it causes an infinite loop in clk_divider_bestdiv() because _next_div() will never return a value greater than maxdiv. Instead of returning table's max divider, this patch returns INT_MAX. Reported-by:Fabio Estevam <festevam@gmail.com> Reported-by:
Shawn Guo <shawn.guo@freescale.com> Tested-by:
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Geert Uytterhoeven authored
- Limit ruler to 80 characters (was: 81), - Widen rate column by 1 for nicer spacing, - Right-align numbers and their column headers, - Move a newline to reduce the number of seq_printf() calls, - Use set_puts() for fixed strings. Before: clock enable_cnt prepare_cnt rate accuracy --------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 After: clock enable_cnt prepare_cnt rate accuracy -------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Heiko Stuebner authored
From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by:
Heiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by:
Thomas Abraham <thomas.ab@samsung.com> Acked-by:
Max Schwarz <max.schwarz@online.de> Tested-by:
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Ulrich Hecht authored
Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by:
Geert Uytterhoeven <geert@linux-m68k.org> Acked-by:
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Andrew Bresticker authored
Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by:
Jim Lin <jilin@nvidia.com> Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
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Andrew Bresticker authored
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by:
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Jim Lin authored
The parent-to-index mapping for xusb_fs_src is incorrect. Fix it by adding a mux table. Signed-off-by:
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Jim Lin authored
Enable hardware control of PLLE spread-spectrum, IDDQ, and enable controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE will use these controls for power-saving optimizations. Signed-off-by:
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Anders Berg authored
Add clk driver to support clock blocks found on the AXM55xx devices. The driver provides clock implementations for three different types of clock devices on the AXM55xx device: PLL clock, a clock divider and a clock mux. Signed-off-by:
Anders Berg <anders.berg@lsi.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by:
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Laurent Pinchart authored
The MSTP[SC]R registers have clock stop bits, not clock enable bits. The bit value should thus be inverted in the is_enabled() operation. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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- 22 May, 2014 1 commit
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Sylwester Nawrocki authored
This patch adds of_clk_get_by_clkspec() helper function, which does only a struct clk lookup from the clock providers. It is used in the subsequent patch where parsing of a clock from device tree and the lookup from providers needed to be split. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
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- 21 May, 2014 2 commits
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Linus Walleij authored
The IM-PD1 PrimeCells all have pclk assignments though this clock cannot be controlled, and we need to provide this as a dummy clock for the PL061 GPIO driver to probe, so let's assign it to all the cells on the board. Signed-off-by:
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Linus Torvalds authored
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