- 21 Sep, 2010 32 commits
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Track if the gpu requires the fence for the execution of a batch buffer and so only wait upon the retirement of the object's last rendering seqno if the fence is in use by the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
Always PAGE_SIZE and only complicates the code. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
The compiler happily does that for us. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
Documentation explicitly mentions that the ring registers are designed to have the same offsets relative to a base registers. Use this to fight the code beaurocratic in intel_ringbuffer.c. No code changes in this patch, just the new definitions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Daniel Vetter authored
This looks like a copy-paste remnant from the i810. All the regs that are actually used are already defined somewhere else in i915_reg.h! Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Use the ring abstraction to hide the details of having choose the appropriate flushing method. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Xiang, Haihao authored
This ring buffer is used for video decoding/encoding on Sandybridge. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
As noted by Zhenyu, we can now simply replace the existing advance hook by calling the new set_tail function pointer directly. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Xiang, Haihao authored
This is prepared for video codec ring buffer on Sandybridge. It is needed to read/write more than one register to move the tail pointer of the video codec ring on Sandybridge. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Xiang, Haihao authored
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer for ring initialization. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Xiang, Haihao authored
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Previously we only tidied up the active bo lists for chipsets were we would attempt to reset the GPU. However, this action is necessary for the system to continue and reclaim the dead bo for all chipsets. Pointed out, in passing, by Owain Ainsworth. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Clear the GPU read domain for the inactive objects on a reset so that they are correctly invalidated on reuse. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Owain Ainsworth noticed that the reset code failed to clear the flushing list leaving the driver in an inconsistent state following a hung GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Change the semantics to retire any buffer older than the current seqno rather than repeatedly calling calling the function to retire the buffer at the head of the list matching the request seqno. Whilst this should have no semantic impact on the implementation, Daniel was wondering if there was a bug where we might miss a retirement and so end up with a continually growing active list. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
On more recent chipsets, restoring the display is not as simple as writing a few registers, so force a full modeset of the current configuration in order to retrain the display link. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Kenneth Graunke authored
Ironlake's graphics reset register has to be accessed via the MCHBAR, rather than via PCI config space, which requires some refactoring. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Kenneth Graunke authored
The graphics domains are listed as GRDOM in the documentation, and the GDRST PCI config register (0xc0) is only valid on I965 and GM45. Newer chips (like Sandy Bridge) have a different GDRST. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Kenneth Graunke authored
Previously, it was only being set if passed GDRST_FULL - but the only caller passed GDRST_RENDER. So the hardware never actually reset. The comments also did not match the code. Instead, just set the reset bit regardless of what flags were passed. The GPU now resets correctly on my GM45. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
We assume that the panel is permenantly connected and that the EDID data is consistent from boot, so simply cache the whole EDID for the panel. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson authored
Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/i915/intel_crt.c
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Chris Wilson authored
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- 20 Sep, 2010 8 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6Linus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6: Staging: vt6655: fix buffer overflow Revert: "Staging: batman-adv: Adding netfilter-bridge hooks"
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6Linus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: USB: musb: MAINTAINERS: Fix my mail address USB: serial/mos*: prevent reading uninitialized stack memory USB: otg: twl4030: fix phy initialization(v1) USB: EHCI: Disable langwell/penwell LPM capability usb: musb_debugfs: don't use the struct file private_data field with seq_files
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6Linus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6: serial: mfd: fix bug in serial_hsu_remove() serial: amba-pl010: fix set_ldisc
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Dan Carpenter authored
"param->u.wpa_associate.wpa_ie_len" comes from the user. We should check it so that the copy_from_user() doesn't overflow the buffer. Also further down in the function, we assume that if "param->u.wpa_associate.wpa_ie_len" is set then "abyWPAIE[0]" is initialized. To make that work, I changed the test here to say that if "wpa_ie_len" is set then "wpa_ie" has to be a valid pointer or we return -EINVAL. Oddly, we only use the first element of the abyWPAIE[] array. So I suspect there may be some other issues in this function. Signed-off-by: Dan Carpenter <error27@gmail.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Sven Eckelmann authored
This reverts commit 96d592ed. The netfilter hook seems to be misused and may leak skbs in situations when NF_HOOK returns NF_STOLEN. It may not filter everything as expected. Also the ethernet bridge tables are not yet capable to understand batman-adv packet correctly. It was only added for testing purposes and can be removed again. Reported-by: Vasiliy Kulikov <segooon@gmail.com> Signed-off-by: Sven Eckelmann <sven.eckelmann@gmx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Feng Tang authored
Medfield HSU driver deal with 4 pci devices(3 uart ports + 1 dma controller), so in pci remove func, we need handle them differently Signed-off-by: Feng Tang <feng.tang@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Mika Westerberg authored
Commit d87d9b7d ("tty: serial - fix tty referencing in set_ldisc") changed set_ldisc to take ldisc number as parameter. This patch fixes AMBA PL010 driver according the new prototype. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Cc: Alan Cox <alan@linux.intel.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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