1. 23 Jun, 2015 6 commits
    • Arun Siluvery's avatar
      drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround · c82435bb
      Arun Siluvery authored
      In Indirect context w/a batch buffer,
      +WaFlushCoherentL3CacheLinesAtContextSwitch:bdw
      
      v2: Add LRI commands to set/reset bit that invalidates coherent lines,
      update WA to include programming restrictions and exclude CHV as
      it is not required (Ville)
      
      v3: Avoid unnecessary read when it can be done by reading register once (Chris).
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Signed-off-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
      Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
      Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      c82435bb
    • Arun Siluvery's avatar
      drm/i915/gen8: Add WaDisableCtxRestoreArbitration workaround · 7ad00d1a
      Arun Siluvery authored
      In Indirect and Per context w/a batch buffer,
      +WaDisableCtxRestoreArbitration
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Signed-off-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
      Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
      Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      7ad00d1a
    • Arun Siluvery's avatar
      drm/i915/gen8: Re-order init pipe_control in lrc mode · c4db7599
      Arun Siluvery authored
      Some of the WA applied using WA batch buffers perform writes to scratch page.
      In the current flow WA are initialized before scratch obj is allocated.
      This patch reorders intel_init_pipe_control() to have a valid scratch obj
      before we initialize WA.
      
      v2: Check for valid scratch page before initializing WA as some of them
      perform writes to it.
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
      Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      c4db7599
    • Arun Siluvery's avatar
      drm/i915/gen8: Add infrastructure to initialize WA batch buffers · 17ee950d
      Arun Siluvery authored
      Some of the WA are to be applied during context save but before restore and
      some at the end of context save/restore but before executing the instructions
      in the ring, WA batch buffers are created for this purpose and these WA cannot
      be applied using normal means. Each context has two registers to load the
      offsets of these batch buffers. If they are non-zero, HW understands that it
      need to execute these batches.
      
      v1: In this version two separate ring_buffer objects were used to load WA
      instructions for indirect and per context batch buffers and they were part
      of every context.
      
      v2: Chris suggested to include additional page in context and use it to load
      these WA instead of creating separate objects. This will simplify lot of things
      as we need not explicity pin/unpin them. Thomas Daniel further pointed that GuC
      is planning to use a similar setup to share data between GuC and driver and
      WA batch buffers can probably share that page. However after discussions with
      Dave who is implementing GuC changes, he suggested to use an independent page
      for the reasons - GuC area might grow and these WA are initialized only once and
      are not changed afterwards so we can share them share across all contexts.
      
      The page is updated with WA during render ring init. This has an advantage of
      not adding more special cases to default_context.
      
      We don't know upfront the number of WA we will applying using these batch buffers.
      For this reason the size was fixed earlier but it is not a good idea. To fix this,
      the functions that load instructions are modified to report the no of commands
      inserted and the size is now calculated after the batch is updated. A macro is
      introduced to add commands to these batch buffers which also checks for overflow
      and returns error.
      We have a full page dedicated for these WA so that should be sufficient for
      good number of WA, anything more means we have major issues.
      The list for Gen8 is small, same for Gen9 also, maybe few more gets added
      going forward but not close to filling entire page. Chris suggested a two-pass
      approach but we agreed to go with single page setup as it is a one-off routine
      and simpler code wins.
      
      One additional option is offset field which is helpful if we would like to
      have multiple batches at different offsets within the page and select them
      based on some criteria. This is not a requirement at this point but could
      help in future (Dave).
      
      Chris provided some helpful macros and suggestions which further simplified
      the code, they will also help in reducing code duplication when WA for
      other Gen are added. Add detailed comments explaining restrictions.
      Use do {} while(0) for wa_ctx_emit() macro.
      
      (Many thanks to Chris, Dave and Thomas for their reviews and inputs)
      
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Signed-off-by: default avatarRafael Barbalho <rafael.barbalho@intel.com>
      Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      17ee950d
    • Chris Wilson's avatar
      drm/i915: Report an error when i915.reset prevents a reset · b1330fbb
      Chris Wilson authored
      If the user disables the GPU reset using the i915.reset parameter and
      one occurs, report that we failed to reset the GPU. If we return early,
      as we currently do, then we leave all state intact (with a hung GPU)
      and clients block forever waiting for their requests to complete.
      
      Testcase: igt/gem_eio
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      [danvet: Mark i915.reset as an unsafe modoption, as discussed with
      Chris.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b1330fbb
    • Daniel Vetter's avatar
      drm/i915: Fix up KMS Kconfig removal patch · bf13af56
      Daniel Vetter authored
      The module pciid list got lost, but somehow most distros seem to
      force-load drm drivers early and no one noticed for a while.
      
      Bug introduced in
      
      commit fd930478
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Fri Jun 19 20:27:27 2015 +0100
      
          drm/i915: Remove KMS Kconfig option
      Reported-by: default avatarTvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
      Cc: Damien Lespiau <damien.lespiau@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
      bf13af56
  2. 22 Jun, 2015 29 commits
  3. 19 Jun, 2015 1 commit
  4. 18 Jun, 2015 2 commits
    • Mika Kuoppala's avatar
      drm/i915: Reset request handling for gen8+ · 7fd2d269
      Mika Kuoppala authored
      In order for gen8+ hardware to guarantee that no context switch
      takes place during engine reset and that current context is properly
      saved, the driver needs to notify and query hw before commencing
      with reset.
      
      There are gpu hangs where the engine gets so stuck that it never will
      report to be ready for reset. We could proceed with reset anyway, but
      with some hangs with skl, the forced gpu reset will result in a system
      hang. By inspecting the unreadiness for reset seems to correlate with
      the probable system hang.
      
      We will only proceed with reset if all engines report that they
      are ready for reset. If root cause for system hang is found and
      can be worked around with another means, we can reconsider if
      we can reinstate full reset for unreadiness case.
      
      v2: -EIO, Recovery, gen8 (Chris, Tomas, Daniel)
      v3: updated commit msg
      v4: timeout_ms, simpler error path (Chris)
      
      References: https://bugs.freedesktop.org/show_bug.cgi?id=89959
      References: https://bugs.freedesktop.org/show_bug.cgi?id=90854
      Testcase: igt/gem_concurrent_blit/prw-blt-overwrite-source-read-rcs-forked
      Testcase: igt/gem_concurrent_blit/gtt-blt-overwrite-source-read-rcs-forked
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Tomas Elf <tomas.elf@intel.com>
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      7fd2d269
    • Vandana Kannan's avatar
      drm/i915/bxt: eDP Panel Power sequencing · b0a08bec
      Vandana Kannan authored
      Changes for BXT - added a IS_BROXTON check to use the macro related to PPS
      registers for BXT.
      BXT does not have PP_DIV register. Making changes to handle this.
      Second set of PPS registers have been defined but will be used when VBT
      provides a selection between the 2 sets of registers.
      
      v2:
      [Jani] Added 2nd set of PPS registers and the macro
      Jani's review comments
      	- remove reference in i915_suspend.c
      	- Use BXT PP macro
      Squashing all PPS related patches into one.
      
      v3: Jani's review comments addressed
      	- Use pp_ctl instead of pp
      	- ironlake_get_pp_control() is not required for BXT
      	- correct the use of && in the print statement
      	- drop the shift in the print statement
      
      v4: Jani's comments
      	- modify ironlake_get_pp_control() - dont set unlock key for bxt
      
      v5: Sonika's comments addressed
      	- check alignment
      	- move pp_ctrl_reg write (after ironlake_get_pp_control())
      	to !IS_BROXTON case.
      	- check before subtracting 1 for t11_t12
      Signed-off-by: default avatarVandana Kannan <vandana.kannan@intel.com>
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Reviewed-by: default avatarSonika Jindal <sonika.jindal@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b0a08bec
  5. 17 Jun, 2015 1 commit
    • Matt Roper's avatar
      drm/i915: Use helper to set CRTC state's mode · ce52299c
      Matt Roper authored
      We need to call drm_atomic_set_mode_for_crtc() rather than copying the
      mode in manually.  As of commit
      
              commit 99cf4a29
              Author: Daniel Stone <daniels@collabora.com>
              Date:   Mon May 25 19:11:51 2015 +0100
      
                  drm/atomic: Add current-mode blob to CRTC state
      
      the helper now also takes care of setting up the mode property blob for
      us; if we don't use the helper and never setup the mode blob, this will
      also trigger a failure in drm_atomic_crtc_check() when we have the
      DRIVER_ATOMIC flag set (i.e., when using the nuclear pageflip support
      via i915.nuclear_pageflip kernel command line parameter).
      
      Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
      Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      ce52299c
  6. 15 Jun, 2015 1 commit