- 31 Mar, 2017 1 commit
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Arnd Bergmann authored
Merge tag 'uniphier-dt-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt Pull "UniPhier ARM SoC DT updates for v4.12" from Masahiro Yamada: - Remove skeleton.dtsi inclusion - Fix W=* build warnings - Fix eMMC pin-mux node - Add pagesize properties to EEPROM nodes * tag 'uniphier-dt-v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: ARM: dts: uniphier: add pagesize property to EEPROM of proto boards ARM: dts: uniphier: add pagesize property to EEPROM of Support Card ARM: dts: uniphier: fix pin groups of eMMC pin-mux node ARM: dts: uniphier: move memory node below aliases node ARM: dts: uniphier: fix no unit name warnings ARM: dts: uniphier: remove skeleton.dtsi inclusion
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- 22 Mar, 2017 6 commits
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Olof Johansson authored
Merge tag 'renesas-dt-bindings-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Renesas ARM Based SoC DT Bindings Updates for v4.12 * Document RZ/G1N and RZ/G1H SoC DT bindings * tag 'renesas-dt-bindings-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Document RZ/G1N SoC DT binding ARM: shmobile: Document RZ/G1H SoC DT binding Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Renesas ARM Based SoC DT Updates for v4.12 Cleanup: * Drop superfluous status update for frequency override on various boards * Always use status "okay" to enable devices on porger board * Add INTC-SYS clock to device tree of various SoCs * Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs * Remove unit-address and reg from integrated cache on various SoCs * Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS * Fix SCIFB0 dmas indentation on r8a774[35] SoCs Enhancements: * Add watchdog timer to r7s72100 SoC * Update sdhi clock bindings on r7s72100 SoC * tag 'renesas-dt-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (31 commits) ARM: dts: silk: Drop superfluous status update for frequency override ARM: dts: alt: Drop superfluous status update for frequency override ARM: dts: gose: Drop superfluous status update for frequency override ARM: dts: porter: Drop superfluous status update for frequency override ARM: dts: koelsch: Drop superfluous status updates for frequency overrides ARM: dts: lager: Drop superfluous status update for frequency override ARM: dts: marzen: Drop superfluous status update for frequency override ARM: dts: bockw: Drop superfluous status update for frequency override ARM: dts: porter: Always use status "okay" to enable devices ARM: dts: r8a7793: Add INTC-SYS clock to device tree ARM: dts: r8a7793: Tidyup Audio-DMAC channel for DVC ARM: dts: r8a7791: Tidyup Audio-DMAC channel for DVC ARM: dts: r8a7794: Add INTC-SYS clock to device tree ARM: dts: r8a7792: Add INTC-SYS clock to device tree ARM: dts: r8a7791: Add INTC-SYS clock to device tree ARM: dts: r8a7790: Add INTC-SYS clock to device tree ARM: dts: r8a73a4: Add INTC-SYS clock to device tree ARM: dts: r7s72100: Add watchdog timer ARM: dts: r8a7790: Tidyup Audio-DMAC channel for DVC ARM: dts: r8a7794: Remove unit-address and reg from integrated cache ... Signed-off-by: Olof Johansson <olof@lixom.net>
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Linus Walleij authored
The moxart interrupt line flags were not respected in previous driver: instead of assigning them per-consumer, a fixes mask was set in the controller. With the migration to a standard Faraday driver we need to set up and handle the consumer flags correctly. Also remove the Moxart-specific flags when switching to using real consumer flags. Extend the register window to 0x100 bytes as we may have a few more registers in there and it doesn't hurt. Tested-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
* shared/dt-symlinks: arm64: dts: add arm/arm64 include symlinks ARM: dts: add arm/arm64 include symlinks Signed-off-by: Olof Johansson <olof@lixom.net>
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Heiko Stuebner authored
Allow including of dtsi files in an architecture-independent manner. Some dtsi files may be shared between architectures and one suggestion was to have symlinks and let these includes get accessed via a #include <arm64/foo.dtsi> So add the necessary symlinks for arm32. Suggested-by: Olof Johansson <olof@lixom.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Olof Johansson <olof@lixom.net>
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Heiko Stuebner authored
Allow including of dtsi files in an architecture-independent manner. Some dtsi files may be shared between architectures and one suggestion was to have symlinks and let these includes get accessed via a #include <arm64/foo.dtsi> So add the necessary symlinks for arm32. Suggested-by: Olof Johansson <olof@lixom.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Olof Johansson <olof@lixom.net>
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- 13 Mar, 2017 15 commits
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Olof Johansson authored
Merge tag 'gemini-dts-base' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt Base patches for Gemini device trees: - Bindings for the platform. - Device trees for everything that was available as board files previously. - New device tree for my target system SQ201. - Device tree bindings for the watchdog. The driver was merged to the watchdog subsystem so this was probably just missed by the maintainer, and it is ACKed by Rob Herring. * tag 'gemini-dts-base' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: add watchdog to the Gemini watchdog: add DT bindings for Cortina Gemini ARM: dts: add a devicetree for Wiliboard WBD-222 ARM: dts: add a devicetree for Wiliboard WBD-111 ARM: dts: add a devicetree for Teltonika RUT1xx ARM: dts: add a devicetree for Raidsonic NAS IB-4220-B ARM: dts: add device tree for Gemini SoC and SQ201 ARM: dts: add top-level DT bindings for Cortina Gemini Signed-off-by: Olof Johansson <olof@lixom.net>
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Masahiro Yamada authored
ST's spec says the page size of 24C64 is 32 byte. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Microchip's spec says the page size of 24LC128 is 64 byte. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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Geert Uytterhoeven authored
Document the RZ/G1N (r8a7744) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Document the RZ/G1H (r8a7742) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7794.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7794.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7793.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The pcie_bus_clk device node is already enabled in r8a7791.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The scif_clk and pcie_bus_clk device nodes are already enabled in r8a7791.dtsi, so there is no need to update their statuses again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7790.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7779.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
The scif_clk device node is already enabled in r8a7778.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
While status "ok" does work, the canonical form is "okay", so update the few places that used the former. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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- 12 Mar, 2017 13 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/s390/linuxLinus Torvalds authored
Pull s390 fixes from Martin Schwidefsky: - four patches to get the new cputime code in shape for s390 - add the new statx system call - a few bug fixes * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux: s390: wire up statx system call KVM: s390: Fix guest migration for huge guests resulting in panic s390/ipl: always use load normal for CCW-type re-IPL s390/timex: micro optimization for tod_to_ns s390/cputime: provide archicture specific cputime_to_nsecs s390/cputime: reset all accounting fields on fork s390/cputime: remove last traces of cputime_t s390: fix in-kernel program checks s390/crypt: fix missing unlock in ctr_paes_crypt on error path
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Thomas Gleixner: - a fix for the kexec/purgatory regression which was introduced in the merge window via an innocent sparse fix. We could have reverted that commit, but on deeper inspection it turned out that the whole machinery is neither documented nor robust. So a proper cleanup was done instead - the fix for the TLB flush issue which was discovered recently - a simple typo fix for a reboot quirk * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/tlb: Fix tlb flushing when lguest clears PGE kexec, x86/purgatory: Unbreak it and clean it up x86/reboot/quirks: Fix typo in ASUS EeeBook X205TA reboot quirk
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull irq fixes from Thomas Gleixner: - a workaround for a GIC erratum - a missing stub function for CONFIG_IRQDOMAIN=n - fixes for a couple of type inconsistencies * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/crossbar: Fix incorrect type of register size irqchip/gicv3-its: Add workaround for QDF2400 ITS erratum 0065 irqdomain: Add empty irq_domain_check_msi_remap irqchip/crossbar: Fix incorrect type of local variables
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Linus Walleij authored
This adds watchdog support to the Gemini SoC DTSI file. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This adds DT bindings for the Cortina systems Gemini SoC watchdog timer. Cc: devicetree@vger.kernel.org Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This devicetree is simply based on the board file in arch/arm/mach-gemini/board-wbd222.c and contain the equivalent platform data, mainly just moving the GPIOs from the global numberspace to explicitly reference their parent GPIO. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This devicetree is simply based on the board file in arch/arm/mach-gemini/board-wbd111.c and contain the equivalent platform data, mainly just moving the GPIOs from the global numberspace to explicitly reference their parent GPIO. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This devicetree is simply based on the board file in arch/arm/mach-gemini/board-rut1xx.c and contain the equivalent platform data, mainly just moving the GPIOs from the global numberspace to explicitly reference their parent GPIO. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This devicetree is simply based on the board file in arch/arm/mach-gemini/board-nas4220b.c and contain the equivalent platform data, mainly just moving the GPIOs from the global numberspace to explicitly reference &gpio1. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This adds a device tree for the Gemini SoC and the ITian Square One SQ201 board that has been my testing target for Gemini device tree support. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij authored
This adds the top level SoC bindings for Cortina systems Gemini platforms. Cc: Janos Laube <janos.dev@gmail.com> Cc: Paulius Zaleckas <paulius.zaleckas@gmail.com> Cc: Hans Ulli Kroll <ulli.kroll@googlemail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Daniel Borkmann authored
Fengguang reported random corruptions from various locations on x86-32 after commits d2852a22 ("arch: add ARCH_HAS_SET_MEMORY config") and 9d876e79 ("bpf: fix unlocking of jited image when module ronx not set") that uses the former. While x86-32 doesn't have a JIT like x86_64, the bpf_prog_lock_ro() and bpf_prog_unlock_ro() got enabled due to ARCH_HAS_SET_MEMORY, whereas Fengguang's test kernel doesn't have module support built in and therefore never had the DEBUG_SET_MODULE_RONX setting enabled. After investigating the crashes further, it turned out that using set_memory_ro() and set_memory_rw() didn't have the desired effect, for example, setting the pages as read-only on x86-32 would still let probe_kernel_write() succeed without error. This behavior would manifest itself in situations where the vmalloc'ed buffer was accessed prior to set_memory_*() such as in case of bpf_prog_alloc(). In cases where it wasn't, the page attribute changes seemed to have taken effect, leading to the conclusion that a TLB invalidate didn't happen. Moreover, it turned out that this issue reproduced with qemu in "-cpu kvm64" mode, but not for "-cpu host". When the issue occurs, change_page_attr_set_clr() did trigger a TLB flush as expected via __flush_tlb_all() through cpa_flush_range(), though. There are 3 variants for issuing a TLB flush: invpcid_flush_all() (depends on CPU feature bits X86_FEATURE_INVPCID, X86_FEATURE_PGE), cr4 based flush (depends on X86_FEATURE_PGE), and cr3 based flush. For "-cpu host" case in my setup, the flush used invpcid_flush_all() variant, whereas for "-cpu kvm64", the flush was cr4 based. Switching the kvm64 case to cr3 manually worked fine, and further investigating the cr4 one turned out that X86_CR4_PGE bit was not set in cr4 register, meaning the __native_flush_tlb_global_irq_disabled() wrote cr4 twice with the same value instead of clearing X86_CR4_PGE in the first write to trigger the flush. It turned out that X86_CR4_PGE was cleared from cr4 during init from lguest_arch_host_init() via adjust_pge(). The X86_FEATURE_PGE bit is also cleared from there due to concerns of using PGE in guest kernel that can lead to hard to trace bugs (see bff672e6 ("lguest: documentation V: Host") in init()). The CPU feature bits are cleared in dynamic boot_cpu_data, but they never propagated to __flush_tlb_all() as it uses static_cpu_has() instead of boot_cpu_has() for testing which variant of TLB flushing to use, meaning they still used the old setting of the host kernel. Clearing via setup_clear_cpu_cap(X86_FEATURE_PGE) so this would propagate to static_cpu_has() checks is too late at this point as sections have been patched already, so for now, it seems reasonable to switch back to boot_cpu_has(X86_FEATURE_PGE) as it was prior to commit c109bf95 ("x86/cpufeature: Remove cpu_has_pge"). This lets the TLB flush trigger via cr3 as originally intended, properly makes the new page attributes visible and thus fixes the crashes seen by Fengguang. Fixes: c109bf95 ("x86/cpufeature: Remove cpu_has_pge") Reported-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Cc: bp@suse.de Cc: Kees Cook <keescook@chromium.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: netdev@vger.kernel.org Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: lkp@01.org Cc: Laura Abbott <labbott@redhat.com> Cc: stable@vger.kernel.org Link: http://lkml.kernrl.org/r/20170301125426.l4nf65rx4wahohyl@wfg-t540p.sh.intel.com Link: http://lkml.kernel.org/r/25c41ad9eca164be4db9ad84f768965b7eb19d9e.1489191673.git.daniel@iogearbox.netSigned-off-by: Thomas Gleixner <tglx@linutronix.de>
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- 11 Mar, 2017 5 commits
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git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull KVM fixes from Radim Krčmář: "ARM updates from Marc Zyngier: - vgic updates: - Honour disabling the ITS - Don't deadlock when deactivating own interrupts via MMIO - Correctly expose the lact of IRQ/FIQ bypass on GICv3 - I/O virtualization: - Make KVM_CAP_NR_MEMSLOTS big enough for large guests with many PCIe devices - General bug fixes: - Gracefully handle exception generated with syndroms that the host doesn't understand - Properly invalidate TLBs on VHE systems x86: - improvements in emulation of VMCLEAR, VMX MSR bitmaps, and VCPU reset * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: nVMX: do not warn when MSR bitmap address is not backed KVM: arm64: Increase number of user memslots to 512 KVM: arm/arm64: Remove KVM_PRIVATE_MEM_SLOTS definition that are unused KVM: arm/arm64: Enable KVM_CAP_NR_MEMSLOTS on arm/arm64 KVM: Add documentation for KVM_CAP_NR_MEMSLOTS KVM: arm/arm64: VGIC: Fix command handling while ITS being disabled arm64: KVM: Survive unknown traps from guests arm: KVM: Survive unknown traps from guests KVM: arm/arm64: Let vcpu thread modify its own active state KVM: nVMX: reset nested_run_pending if the vCPU is going to be reset kvm: nVMX: VMCLEAR should not cause the vCPU to shut down KVM: arm/arm64: vgic-v3: Don't pretend to support IRQ/FIQ bypass arm64: KVM: VHE: Clear HCR_TGE when invalidating guest TLBs
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git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linuxLinus Torvalds authored
Pull extable.h fix from Paul Gortmaker: "Fixup for arch/score after extable.h introduction. It seems that Guenter is the only one on the planet doing builds for arch/score -- we don't have compile coverage for it in linux-next or in the kbuild-bot either. Guenter couldn't even recall where he got his toolchain, but was kind enough to share it with me so I could validate this change and also add arch/score to my build coverage. I sat on this a bit in case there was any other fallout in other arch dirs, but since this still seems to be the only one, I might as well send it on its way" * tag 'extable-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux: score: Fix implicit includes now failing build after extable change
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git://git.kernel.org/pub/scm/linux/kernel/git/tytso/randomLinus Torvalds authored
Pull random updates from Ted Ts'o: "Change get_random_{int,log} to use the CRNG used by /dev/urandom and getrandom(2). It's faster and arguably more secure than cut-down MD5 that we had been using. Also do some code cleanup" * tag 'random_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/random: random: move random_min_urandom_seed into CONFIG_SYSCTL ifdef block random: convert get_random_int/long into get_random_u32/u64 random: use chacha20 for get_random_int/long random: fix comment for unused random_min_urandom_seed random: remove variable limit random: remove stale urandom_init_wait random: remove stale maybe_reseed_primary_crng
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Guenter Roeck authored
After changing from module.h to extable.h, score builds fail with: arch/score/kernel/traps.c: In function 'do_ri': arch/score/kernel/traps.c:248:4: error: implicit declaration of function 'user_disable_single_step' arch/score/mm/extable.c: In function 'fixup_exception': arch/score/mm/extable.c:32:38: error: dereferencing pointer to incomplete type arch/score/mm/extable.c:34:24: error: dereferencing pointer to incomplete type because extable.h doesn't drag in the same amount of headers as the module.h did. Add in the headers which were implicitly expected. Fixes: 90858794 ("module.h: remove extable.h include now users have migrated") Signed-off-by: Guenter Roeck <linux@roeck-us.net> [PG: tweak commit log; refresh for sched header refactoring.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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Masahiro Yamada authored
The eMMC devices on UniPhier boards are generally used in the 8-bit mode. So, DAT4-7 pins should be controlled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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