- 09 Dec, 2013 20 commits
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Jean-Christophe PLAGNIOL-VILLARD authored
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Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> [nicolas.ferre@atmel.com: remove one macb node too many] Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Nicolas Ferre authored
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Nicolas Ferre authored
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Boris BREZILLON <b.brezillon@overkiz.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Update to production one. Signed-off-by:
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Ludovic Desroches authored
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Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by:
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Ludovic Desroches authored
pinctrl-names property was missing from mmc nodes. Cc: <stable@vger.kernel.org> #3.11+ Signed-off-by:
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Bo Shen authored
Enable qt1070 keyboard as a wakeup source on sama5d3xek board. Signed-off-by:
Bo Shen <voice.shen@atmel.com> Signed-off-by:
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Rodolfo Giometti authored
This patch adds the Cosino at91sam9g35 based CPU module and the Cosino Mega 2560 extension board. Web site: http://www.cosino.itSigned-off-by:
Rodolfo Giometti <giometti@linux.it> [plagnioj@jcrosoft.com: added "at91-" to files, pinctrl fixed, removed unneeded stuff] Acked-by:
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Nicolas Ferre authored
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Nicolas Ferre authored
Change the sha/aes/tdes compatibility string to match common case for the at91sam9g45 family which is to keep the at91 prefix. Signed-off-by: -
Nicolas Ferre authored
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Jean-Christophe PLAGNIOL-VILLARD authored
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Jean-Christophe PLAGNIOL-VILLARD authored
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Jean-Christophe PLAGNIOL-VILLARD authored
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Jean-Christophe PLAGNIOL-VILLARD authored
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Nicolas Ferre authored
The "atmel,at91rm9200-sdramc" was missing from binding documentation. Signed-off-by:
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Nicolas Ferre authored
In response to the "undocumented compatible strings" message, here is a patch which is adding the precision of two "chips" that should be used for the "atmel,<chip>-aic" compatibility string. Signed-off-by:
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Boris BREZILLON authored
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Boris BREZILLON authored
Add ethernet phy node in at91rm9200ek.dts. The reg register is not specified, as it may differ depending on the init process of the board: ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy will take its address from these pins during the reset process. The macb driver will launch a full scan on the mdio bus to discover the phy address. Signed-off-by:
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Nicolas Ferre authored
Swap names as they were improperly defined. Signed-off-by:
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- 02 Dec, 2013 20 commits
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Boris BREZILLON authored
This patch removes the old main clk node which is now useless as sama5d3 SoCs and boards are no longer compatible with the old at91 clk implementations. It also remove old clock definitions (clock definitions using at91 old clk framework). Signed-off-by:
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Boris BREZILLON authored
This patch removes the selection of AT91_USE_OLD_CLK when selecting sama5d3 SoC support. This will enable automatically enable COMMON_CLK_AT91 option and add support for at91 common clk implementation. Signed-off-by:
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Boris BREZILLON authored
Define the main clock frequency for the new main clock node in sama5d3xcm.dtsi. Signed-off-by:
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Boris BREZILLON authored
Define sama5d3 clocks in sama5d3 device tree. Add references to the appropriate clocks in each peripheral. Signed-off-by:
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Boris BREZILLON authored
This patch encloses sama5d3 old clk registration in "#if defined(CONFIG_OLD_CLK_AT91) #endif" sections. Signed-off-by:
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Boris BREZILLON authored
This patch prepare the transition to common clk for sama5 dt boards by replacing the timer init callback. Clocks registration cannot be done in early init callback (as formerly done by the old clk implementation) because it requires dynamic allocation which is not ready yet during early init. In the other hand, at91 clocks must be registered before at91sam926x_pit_init is called because PIT (Periodic Interval Timer) driver request the master clk (mck). A new function (at91sama5_dt_timer_init) is created to fullfil these needs. This function registers all at91 clks using the dt definition before calling the PIT init function. The device tree clock registration is enabled only if common clk is selected. Else the old clk registration is been done during at91_dt_initialize call. Signed-off-by:
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Boris BREZILLON authored
This patch adds new compatible string for PMC node to prepare the transition to common clk. These compatible string come from pmc driver in clk subsystem and are needed to provide new device tree compatibility with old at91 clks (device tree using common clks will use the new compatible strings). Signed-off-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
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Boris BREZILLON authored
Use device tree to get the source clock of the PIT (Periodic Interval Timer). If the clock is not found in device tree (or dt is not enabled) we'll try to get it using clk_lookup definitions. Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 clks dt bindings documentation. Signed-off-by:
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Boris BREZILLON authored
This patch adds at91 smd (Soft Modem) clock implementation using common clk framework. Not used by any driver right now. Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 usb clock implementation using common clk framework. This clock is used to clock usb ports (ohci, ehci and udc). Signed-off-by:
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Boris BREZILLON authored
This adds new at91 utmi clock implementation using common clk framework. This clock is a pll with a fixed factor (x40). It is used as a source for usb clock. Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 programmable clocks implementation using common clk framework. A programmable clock is a clock which can be exported on a given pin to clock external devices. Each programmable clock is given an id (from 0 to 8). The number of available programmable clocks depends on the SoC you're using. Programmable clock driver only implements the clock setting (clock rate and parent setting). It must be chained to a system clock in order to enable/disable the generated clock. The PCKX pins used to output the clock signals must be assigned to the appropriate peripheral (see atmel's datasheets). Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 peripheral clock implementation using common clk framework. Almost all peripherals provided by at91 SoCs need a clock to work properly. This clock is enabled/disabled using PCER/PCDR resgisters. Each peripheral is given an id (see atmel's datasheets) which is used to define and reference peripheral clocks. Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you can configure the peripheral clock as a division of the master clock. This will help reducing the peripherals power comsumption. Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 system clock implementation using common clk framework. Some peripherals need to enable a "system" clock in order to work properly. Each system clock is given an id based on the bit position in SCER/SCDR registers. Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 master clock implementation using common clk framework. The master clock layout describe the MCKR register layout. There are 2 master clock layouts: - at91rm9200 - at91sam9x5 Master clocks are given characteristics: - min/max clock output rate These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 pll clock implementation using common clk framework. The pll clock layout describe the PLLX register layout. There are four pll clock layouts: - at91rm9200 - at91sam9g20 - at91sam9g45 - sama5d3 PLL clocks are given characteristics: - min/max clock source rate - ranges of valid clock output rates - values to set in out and icpll fields for each supported output range These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by:
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Boris BREZILLON authored
This patch adds new at91 main oscillator clock implementation using common clk framework. If rate is not provided during clock registration it is calculated using the slow clock (main clk parent in this case) rate and MCFR register. Signed-off-by:
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Boris BREZILLON authored
This patch adds a new macro file for PMC macros. This macro file includes the definitions of SR (status register) bit offsets and will be use to reference PMC irqs. Signed-off-by:
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Boris BREZILLON authored
This patch adds at91 PMC (Power Management Controller) base support. All at91 clocks managed by the PMC unit will use this framework. This framework provides the following fonctionalities: - define a new struct at91_pmc to hide PMC internals (lock, PMC memory mapping, irq domain, ...) - read/write helper functions (pmc_read/write) to access PMC registers - lock/unlock helper functions (pmc_lock/unlock) to lock/unlock access to pmc registers - a new irq domain and its associated irq chip to request PMC specific interrupts (useful for clk prepare callbacks) The PMC unit is declared as a dt clk provider (CLK_OF_DECLARE), and every clk using this framework will declare a table of of_at91_clk_init_cb_t and add it to the pmc_clk_ids table. When the pmc dt clock setup function is called (by of_clk_init function), it triggers the registration of every supported child clk (those matching the definitions in pmc_clk_ids). This patch copies at91_pmc_base (memory mapping) and at91sam9_idle (function) from arch/arm/mach-at91/clock.c (which is not compiled if COMMON_CLK_AT91 is enabled). Signed-off-by:
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