- 13 Jun, 2024 12 commits
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Imre Deak authored
Send a modeset-retry uevent to all connectors in the same MST topology after a link training failure and reduction of the link parameters. This matches the way the same uevent is sent after a DP tunnel BW allocation failure. v2: Add NOTE that the atomic state may not be valid for SST links and assert that it's valid for MST links. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-11-imre.deak@intel.com
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Imre Deak authored
The next patch adds sending a modeset-retry uevent after a link training failure to all MST connectors on link. This requires the atomic state, so pass it to intel_dp_start_link_train(). In case of SST where retraining still happens by calling this function directly instead of a modeset commit the atomic state is not available and NULL is passed instead. This is ok, since in this case the encoder's only DP connector is available from intel_dp->attached_connector not requiring the atomic state. v2: Add NOTE that the atomic state may not be valid for SST links and assert that it's valid for MST links. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:Imre Deak <imre.deak@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-10-imre.deak@intel.com
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Imre Deak authored
Try to maintain the current link parameters by retrying the link training with unchanged link parameters before reducing these parameters (sending an uevent to userspace to retrain the link instead). Signed-off-by:
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Imre Deak authored
Recheck the link state after a passing link training, with a 2 sec delay to account for cases where the link goes bad following the link training and the sink doesn't report this via an HPD IRQ. The delayed work added here will be also used by a later patch after a failed link training to try to retrain the link with unchanged link params before reducing the link params. v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports). v3: - Move the helpers to a new intel_encoder.c file, rename them accordingly. (Ville) - Add the work to intel_encoder instead of intel_digital_port. - Call the encoder specific link check function via an encoder hook. - Flush the link check work during encoder destroy from intel_dp_encoder_flush_work(). - Flush the link check work during encoder suspend as well. v4: Call intel_encoder_link_check_init() with a valid encoder pointer. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Imre Deak authored
Instead of direct calls to the link train functions, retrain the link via a commit modeset. The direct call means that the output port will be disabled/re-enabled while the rest of the pipeline (transcoder) is active, which doesn't seem to work on MST at least. It leads to underruns and black screen, presumedly because the transcoder is not disabled/re-enabled along the port. Leave switching to a commit modeset on SST for a later patchset, as that seems to work ok currently (though better to using a commit there too, due to the suppressed underruns). v2: Keep reverse line length order for local variables. (Ville) Reviewed-by:
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Imre Deak authored
Factor out a function to modeset commit a set of pipes, which a later patch will reuse for DP link retraining. Reviewed-by:
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Imre Deak authored
Reduce the indentation in intel_dp_get_link_train_fallback_values() by adding separate helpers to reduce the link rate and lane count. Also simplify things by passing crtc_state to the function. This also prepares for later patches in the patchset adding a limitation on how the link params are reduced. While at it use lt_dbg()/lt_err() for debug/error prints in the function which will also print the connector/encoder prefix and add a debug print about reducing the link parameters. v2: - Align reduce_lane_count()'s error handling flow with reduce_link_rate(). (Ville, Jani) - Use lt_dbg()/lt_err() in the function. Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Imre Deak authored
Move the functions used to reduce the link parameters during link training to intel_dp_link_training.c . Reviewed-by:
Manasi Navare <navaremanasi@chromium.org> Signed-off-by:
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Imre Deak authored
For clarity move the link training parameters updated during link training based on the pass/fail LT result under a substruct in intel_dp. This prepares for later patches in this patchset adding similar params here. Rename intel_dp_reset_max_link_params() to intel_dp_reset_link_params() to better reflect what state gets reset. v2: Add the parameters to a more generic link substruct. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Imre Deak authored
Symbols consisting of multiple (4) TU timeslots may get split across MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1 lane. Atm, we also have to align the PBNs used to allocate BW along the MST path, since DRM core keeps track of its own TU value, derived from the PBN and that TU value must match what the driver calculates. On some platforms the alignment is only required on 8b/10b links, a follow-up patch will remove the limitation for those. Bspec: 49266, 68922 Reviewed-by:
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Imre Deak authored
The branch or sink device decompressing a stream may have a limitation on the input/uncompressed BPP, which is lower than the base line BPP (determined by the sink's EDID). In some cases a stream with an input BPP higher than this limit will be converted automatically by the device decompressing the stream, by truncating the BPP, however in some cases - seen at least in Dell dock's DP->HDMI converters - the decompression will fail. Fix the above by limiting the input BPP correctly. This is done already correctly for SST outputs. Reviewed-by:
Luca Coelho <luciano.coelho@intel.com> Signed-off-by:
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Mitul Golani authored
Compute trans vrr vsync params only when either VRR or CMRR is enabled. Fixes: 5922f453 ("drm/i915/display: Compute vrr vsync params") Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240611120525.148042-1-mitulkumar.ajitkumar.golani@intel.com
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- 12 Jun, 2024 2 commits
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Stanislav Lisovskiy authored
According to BSpec we now should call "master" pipes, "primary" pipes and "slave" pipes, should be "secondary" pipes. Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> [vsyrjala: Don't rename port sync stuff, catch a few more things] Signed-off-by:
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Stanislav Lisovskiy authored
Lets unify both bigjoiner and ultrajoiner under simple "joiner" name, because in future we might have multiple configurations, involving multiple bigjoiners, ultrajoiner, however it is possible to use same api for handling both. v2: - Renamed back some bigjoiner specific parts for now(Ville) Signed-off-by:
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- 11 Jun, 2024 22 commits
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Jouni Högander authored
When checking vblank length used wake time is aux less wake time for eDP Panel Replay (vblank length is not checked for DP2.0 Panel Replay). Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-14-jouni.hogander@intel.com
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Jouni Högander authored
As Lunarlake doesn't have block count configuration vblank should be checked against IO buffer wake time. Bspec: 68920 Signed-off-by:
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Jouni Högander authored
SU SDP scanline indication should be taken into account when checking vblank length. In Bspec we have: PSR2_CTL[ SU SDP scanline indication ] = 0: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start) > PSR2_CTL Block Count Number value in lines PSR2_CTL[ SU SDP scanline indication ] = 1: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start- 1) > PSR2_CTL Block Count Number value in lines Bspec: 49274 Signed-off-by:
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Jouni Högander authored
We are about to add more complexity to vblank length check. It makes sense to move it to separate function for sake of clarity. v2: change name to wake_lines_fit_into_vblank Signed-off-by:
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Jouni Högander authored
Currently Panel Replay status printout is printing frame lock status. It should print Panel Replay status instead. Panel Replay status register field follows PSR status register field. Use existing PSR code for that. Fixes: ef75c25e ("drm/i915/panelreplay: Debugfs support for panel replay") Signed-off-by:
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Jouni Högander authored
Early Transport is possible and in our HW mandatory on eDP Panel Replay. Add parameter to intel_psr2_config_et_valid to differentiate validity check for Panel Replay. v2: fix intel_dp->psr_dpcd[0] check Signed-off-by:
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Jouni Högander authored
Convert intel_alpm_aux_wake_supported and intel_alpm_aux_less_wake_supported as non-static. Use them in intel_psr.c instead of local variables. Signed-off-by:
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Jouni Högander authored
Current intel_psr_enable_sink is a mess due to partly reusing PSR bit definitions for Panel Replay. Even thought PSR and Panel Replay enable registers do have common bits they still have also different bits and same bits with different meaning. For sake of clarity split enabling sink to PSR and Panel Replay specific parts. Also fix issue caused by using psr->panel_replay_enabled to early. Fixes: 88ae6c65 ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by:
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Jouni Högander authored
Add missing Panel Replay Enable SU Region ET bit defined in DP2.1 specification. Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-6-jouni.hogander@intel.com
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Jouni Högander authored
Panel Replay is not enabled if there are no active planes. Do not compare it on pipe comparison. Otherwise we get pipe mismatch. Fixes: ac9ef327 ("drm/i915/psr: Panel replay has to be enabled before link training") Signed-off-by:
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Jouni Högander authored
Currently intel_dp_vsc_sdp_unpack is not taking into account Panel Replay vsc sdp. Fix this by adding vsc sdp revision 0x6 and length 0x10 into intel_dp_vsc_sdp_unpack Signed-off-by:
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Jouni Högander authored
Currently AUX Less Wake lines are not written into ALPM_CTL. Fix this. Fixes: 1ccbf135 ("drm/i915/psr: Enable ALPM on source side for eDP Panel replay") Signed-off-by:
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Jouni Högander authored
We want to have own variables for fast wake lines and aux less wake time. It might be needed to choose if we can enable Panel Replay Selective Update or PSR2. Also currently aux less wake time is overwritten by calculated fast wake time. v2:use aux less wake time in intel_alpm_lobf_compute_config Fixes: da6a9836 ("drm/i915/psr: Calculate aux less wake time") Signed-off-by:
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Mitul Golani authored
Compute Fixed Average Vtotal/CMRR with resepect to userspace VRR enablement. Also calculate required parameters in case of CMRR is enabled. During intel_vrr_compute_config, CMRR is getting enabled based on userspace has enabled Variable refresh mode with VRR timing generator or not. Make CMRR as small subset of FAVT mode, when Panel is running on Fixed refresh rate and on VRR framework then only enable CMRR to match with actual refresh rate. --v2: - Update is_cmrr_frac_required function return as bool, not int. [Jani] - Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani] - Fix typo and usage of camel case in cmrr_get_vtotal. [Jani] - Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani] - Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani] - Correct valiable name usage in is_cmrr_frac_required. [Ville] --v3: - Removing RFC tag. --v4: - Added edp check to address edp usecase for now. (ville) - Updated is_cmrr_fraction_required to more simplified calculation. - on longterm goal to be worked upon uapi as suggestion from ville. --v5: - Correct vtotal paramas accuracy and add 2 digit precision. - Avoid using DIV_ROUND_UP and improve scanline precision. --v6: - Make CMRR a small subset of FAVT mode. --v7: - Update commit message to avoid confusion with Legacy VRR (Ankit). - Add cmrr.enable in last, so remove from this patch. --v8: - Set cmrr.enable in current patch instead of separate patch (Ankit). - Since vrr.enable and cmrr.enable are not mutually exclusive, handle accordingly (Ankit). - is_edp is not required inside is_cmrr_frac_required function (Ankit). - Add video_mode_required flag for future enhancement. - Correct cmrr_m/cmrr_n calculation. --v9: - Move patch to last and set other bits before computing cmrr.enable.(Ankit) - Add TODO: for to address target refresh rate precision as future enhancement. Signed-off-by:
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Mitul Golani authored
Compute vrr vsync params in case of FAVT as well instead of only to AVT mode of operation. --v2: - Remove redundant computation for vrr_vsync_start and vrr_vsync_end(Ankit). --v3: - vrr.enable and cmrr.enable check together is not required as both will be true at the same point in time. (Ankit) - Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit) Signed-off-by:
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Mitul Golani authored
Compute params for Adaptive Sync SDP when Fixed Average Vtotal mode is enabled. --v2: Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit). --v3: - Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit). - check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp. --v4: - Use drm_mode_vrefresh instead of manual calculation (Ankit). Signed-off-by:
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Mitul Golani authored
Add support of pack and unpack for target_rr_divider. --v2: - Set Target Refresh Rate Divider bit when related AS SDP bit is set (Ankit). --v3: - target_rr_divider is bools so set accordingly (Ankit). Signed-off-by:
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Mitul Golani authored
Add target_rr_divider to structure representing AS SDP. It is valid only in FAVT mode, sink device ignores the bit in AVT mode. --v2: - Update commit header and send patch to dri-devel. Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Acked-by:
Maxime Ripard <mripard@kernel.org> Signed-off-by:
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Mitul Golani authored
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable is set, With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling.[Jani] - Correct messed up condition in intel_vrr_enable. [Jani] --v4: - Removing RFC tag. --v5: - CMRR handling in co-existatnce of LRR and DRRS. --v7: - Rebase on top of AS SDP merge. --v8: - Remove cmrr_enabling/disabling and update commit message. (Ankit) --v9: - Revert removed line(Ankit). Signed-off-by:
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Mitul Golani authored
Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR function, with the necessary bitfields. Compute these registers when CMRR is enabled, extending Adaptive refresh rate capabilities. --v2: - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani] - Fix indent and order based on register offset. [Jani] --v3: - Removing RFC tag. --v4: - Update place holder for CMRR register definition. (Jani) --v5: - Add CMRR register definitions to a separate file intel_vrr_reg.h. --v6: - Fixed indentation. (Jani) - Add dependency header intel_display_reg_defs.h. (Jani) - Rename file name to intel_vrr_regs.h instead of reg.h (Jani) --v7: - Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing, as it is already being done during intel_vrr_enable. (Ankit) Signed-off-by:
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Mitul Golani authored
Move VRR related register definitions to a separate file called intel_vrr_regs.h. Signed-off-by:
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Mitul Golani authored
Update the indentation for the VRR register definition and its bits, and fix checkpatch issues to ensure smooth movement of registers and bits. --v2: - Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit). - Fix all indentation related VRR registers and bits instead of checkpatch one. Signed-off-by:
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- 07 Jun, 2024 4 commits
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Balasubramani Vivekanandan authored
Platform descriptor defined and PCI IDs added for Battlemage. Signed-off-by:
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_STEREO_3D_CTL register macro. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/76f980f5ed3638746c6b58dec7d0bd8c43a37987.1717514638.git.jani.nikula@intel.com
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Ville Syrjälä authored
Since BDB version 211 block 46 has included more luminance and gamma related information. Define it fully. The data is semi-based on DisplayID v2.0 apparently. Signed-off-by:
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Ville Syrjälä authored
The VBT spec does a very poor job of defining how the chromaticity coordinates in block 46 are laid out. After double checking the Windows implementation it turns out these more or less match the EDID definition, where the 10bit values are split into 2bit + 8bit chunks. Adjust our struct definition to reflect that. Signed-off-by:
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