- 23 Feb, 2024 37 commits
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
Bo Liu <liubo03@inspur.com> Link: https://lore.kernel.org/r/20240206071314.8721-17-liubo03@inspur.comSigned-off-by:
Lee Jones <lee@kernel.org>
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
Matti Vaittinen <mazziesaccount@gmail.com> Link: https://lore.kernel.org/r/20240206071314.8721-12-liubo03@inspur.comSigned-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20240206071314.8721-11-liubo03@inspur.comSigned-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240206071314.8721-9-liubo03@inspur.comSigned-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Bo Liu authored
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by:
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Ricardo B. Marliere authored
Now that the driver core can properly handle constant struct bus_type, move the mcp_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Suggested-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
"Ricardo B. Marliere" <ricardo@marliere.net> Reviewed-by:
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Charles Keepax authored
Including some missing headers. Suggested-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240129152557.3221212-1-ckeepax@opensource.cirrus.comSigned-off-by:
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Andrew Davis authored
Add TI SERDES control registers compatible. This is a region found in the TI AM65 CTRL_MMR0 register space[0]. Each instance is used to control a SERDES clock and lane select mux. [0] https://www.ti.com/lit/pdf/spruid7Signed-off-by:
Andrew Davis <afd@ti.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240205174736.27749-1-afd@ti.comSigned-off-by:
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Siddharth Vadapalli authored
The PCIE_CTRL registers within the CTRL_MMR space of TI's J784S4 SoC are used to configure the link speed, lane count and mode of operation of the respective PCIe instance. Add compatible for allowing the PCIe driver to obtain a regmap for the PCIE_CTRL register within the System Controller device-tree node in order to configure the PCIe instance accordingly. The Technical Reference Manual for J784S4 SoC with details of the PCIE_CTRL registers is available at: https://www.ti.com/lit/zip/spruj52Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Acked-by:
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Dharma Balasubiramani authored
Convert the atmel,hlcdc binding to DT schema format. Align clocks and clock-names properties to clearly indicate that the LCD controller expects lvds_pll_clk when interfaced with the lvds display. This alignment with the specific hardware requirements ensures accurate device tree configuration for systems utilizing the HLCDC IP. Signed-off-by:
Dharma Balasubiramani <dharma.b@microchip.com> Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240202001733.91455-4-dharma.b@microchip.comSigned-off-by:
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Charles Keepax authored
As it devm_pm_runtime_enable() can fail due to memory allocations, it is best to handle the error. Suggested-by:
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Charles Keepax authored
Use of dev_err_probe() was missed in the i2c and sdw parts of the code, update the missing parts. Suggested-by:
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Charles Keepax authored
Make the defines a little clearer by adding time based postfixes. Suggested-by:
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Charles Keepax authored
__xxx is the preferred type for firmware interfaces. Suggested-by:
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Charles Keepax authored
Use more forward declarations, move header guards to cover other includes, and rely less on including headers through other headers. Suggested-by:
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Maciej Strozek authored
Current code executes only once despite the while loop, so remove the loop. Also msleep(1) will likely result in a larger sleep, so increase its value for clarity while keeping the same behaviour. Signed-off-by:
Maciej Strozek <mstrozek@opensource.cirrus.com> Reviewed-by:
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Simon Horman authored
Although it does not seem to have any untoward side-effects, the use of ';' to separate to assignments seems more appropriate than ','. Flagged by clang-17 -Wcomma No functional change intended. Compile tested only. Signed-off-by:
Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/20240123-rave-sp-comma-v1-1-84e9b15ba205@kernel.orgSigned-off-by:
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Lukasz Majczak authored
Add ChromeOS EC-based watchdog as EC subdevice. Signed-off-by:
Lukasz Majczak <lma@chromium.org> Link: https://lore.kernel.org/r/20240119084328.3135503-4-lma@chromium.orgSigned-off-by:
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Dmitry Baryshkov authored
Add qcom,qcm2290-tcsr and qcom,sm6115-tcsr, compatibles for TCSR blocks on the corresponding platforms. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
dtschema package defines firmware-name as string-array, so individual bindings should not make it a string but instead just narrow the number of expected firmware file names. Signed-off-by:
Jeff LaBundy <jeff@labundy.com> Link: https://lore.kernel.org/r/20240115182042.1610134-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Lee Jones authored
Avoid these nasty W=1 errors: drivers/mfd/omap-usb-host.c: In function ‘usbhs_omap_probe’: drivers/mfd/omap-usb-host.c:706:54: error: ‘_clk’ directive output may be truncated writing 4 bytes into a region of size between 1 and 11 [-Werror=format-truncation=] drivers/mfd/omap-usb-host.c:705:17: note: ‘snprintf’ output between 24 and 34 bytes into a destination of size 30 drivers/mfd/omap-usb-host.c:721:56: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 8 [-Werror=format-truncation=] drivers/mfd/omap-usb-host.c:721:33: note: directive argument in the range [-2147483640, 2147483647] drivers/mfd/omap-usb-host.c:720:17: note: ‘snprintf’ output between 28 and 38 bytes into a destination of size 30 drivers/mfd/omap-usb-host.c:731:55: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 9 [-Werror=format-truncation=] drivers/mfd/omap-usb-host.c:731:33: note: directive argument in the range [-2147483640, 2147483647] drivers/mfd/omap-usb-host.c:730:17: note: ‘snprintf’ output between 27 and 37 bytes into a destination of size 30 Cc: Tony Lindgren <tony@atomide.com> Cc: Keshava Munegowda <keshava_mgowda@ti.com> Cc: Roger Quadros <rogerq@ti.com> Cc: linux-omap@vger.kernel.org Signed-off-by: -
Fuyao Kashizuku authored
The identifiers are used as IRQ resource numbers, where 0 is treated specially. This fixes sun4i-gpadc-iio probe failed when request irq. The backstack: WARNING: CPU: 3 PID: 1 at drivers/base/platform.c:451 __platform_get_irq_byname+0xb8/0xc4 0 is an invalid IRQ number Modules linked in: CPU: 3 PID: 1 Comm: swapper/0 Not tainted 6.7.0-rc6 #9 Hardware name: Allwinner sun8i Family unwind_backtrace show_stack dump_stack_lvl __warn warn_slowpath_fmt __platform_get_irq_byname platform_get_irq_byname sun4i_irq_init sun4i_gpadc_probe platform_probe really_probe __driver_probe_device driver_probe_device __driver_attach bus_for_each_dev bus_add_driver driver_register do_one_initcall do_initcall_level do_initcalls kernel_init_freeable kernel_init Log reports: sun4i-gpadc-iio sun6i-a31-gpadc-iio.0: error -EINVAL: IRQ FIFO_DATA_PENDING not found sun4i-gpadc-iio: probe of sun6i-a31-gpadc-iio.0 failed with error -22 Signed-off-by:
Fuyao Kashizuku <fuyao@sjterm.com> Acked-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/ZYuFbUUus9apiCpq@debian.cygSigned-off-by:
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Ilpo Järvinen authored
Instead of open coding, use ALIGN_DOWN() for alignment. Signed-off-by:
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20231229145059.6138-1-ilpo.jarvinen@linux.intel.comSigned-off-by:
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Aleksandrs Vinarskis authored
Some devices (eg. Dell XPS 9530, 2023) due to a firmware bug have a misconfigured clock divider, which should've been 1:1. This introduces quirk which conditionally re-configures the clock divider to 1:1. Signed-off-by:
Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231221185142.9224-3-alex.vinarskis@gmail.comSigned-off-by:
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Aleksandrs Vinarskis authored
Introduce generic quirk table, and port existing walkaround for select Microsoft devices to it. This is a preparation for QUIRK_CLOCK_DIVIDER_UNITY. Signed-off-by:
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Lee Jones authored
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- 08 Feb, 2024 3 commits
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Biju Das authored
Convert the da9062 PMIC device tree binding documentation to json-schema. Document the missing gpio child node for da9062. While at it, update description with link to product information and example. The missing child node with of_compatible defined in MFD_CELL_OF is causing the below warning message: da9062-gpio: Failed to locate of_node [id: -1] So, make all child nodes with of_compatible defined in struct mfd_cell as required property for da906{1,2} devices. The "gpio-controller" and "#gpio-cells" properties are defined in the parent instead of gpio child node as there are existing driver users based on these parent properties. Signed-off-by:Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Link: https://lore.kernel.org/r/20240131102656.3379-7-biju.das.jz@bp.renesas.comSigned-off-by:
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Biju Das authored
Sort child devices alphabetically. Signed-off-by:
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Biju Das authored
Convert the da906{1,2} thermal device tree binding documentation to json-schema. Update MAINTAINERS entries and description by referring to dlg,da9062-thermal.yaml binding file. Signed-off-by:Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240131102656.3379-5-biju.das.jz@bp.renesas.comSigned-off-by:
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