Merge tag 'highbank-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next/soc

From Rob Herring:
Highbank platform updates for 3.13

- convert Calxeda cpuidle driver to a platform driver and to use PSCI
- convert highbank smp_ops and suspend to PSCI

* tag 'highbank-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  dts: calxeda: add ARM PSCI binding
  ARM: highbank: adapt to use ARM PSCI calls
  ARM: PSCI: remove unnecessary include of arm-gic.h
  cpuidle: calxeda: add support to use PSCI calls
  ARM: highbank: cpuidle: convert to platform driver
  cpuidle: calxeda: add cpu_pm_enter/exit calls

From Jason Cooper:
mvebu soc changes for v3.13 (round 2)

 - kirkwood
    - remove mbus init, pcie clk init
    - retain MAC addr for DT ethernet (work around broken IP)
    - docs: clarify Armada SoCs

* tag 'soc-3.13-2' of git://git.infradead.org/linux-mvebu:
  Documentation: arm/Marvell: clarify Armada SoCs that match 78xx0 pattern
  ARM: kirkwood: retain MAC address for DT ethernet
  ARM: kirkwood: Remove unneeded PCIe clock adding
  ARM: kirkwood: Remove unneeded MBus initialization
  ARM: kirkwood: Add standby support
Signed-off-by: Kevin Hilman <khilman@linaro.org>

Merge tag 'integrator-for-v3.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc

From Linus Walleij:
Integrator patches for the v3.13 kernel cycle:
- Fix up the LED support
- Update the Integrator defconfig
- Remove ATAG boot path
- Move some stuff over to the device tree

* tag 'integrator-for-v3.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
  ARM: integrator: core module registers from compatible strings
  ARM: integrator: use devm_ioremap() to remap CM
  cpufreq: probe the Integrator cpufreq driver from DT
  ARM: integrator: move CM base into device tree
  ARM: integrator: decommission the <mach/irqs.h> header
  ARM: integrator: delete non-devicetree boot path
  ARM: integrator: print the Linux IRQ in LL_DEBUG code
  ARM: integrator: get the LM interrupts from DT
  ARM: integrator: update defconfig
  ARM: integrator: get the CM control register by proxy
Signed-off-by: Kevin Hilman <khilman@linaro.org>

From Sekhar Nori:
* davinci/soc:
  ARM: davinci: convert to clockevents_config_and_register
Signed-off-by: Kevin Hilman <khilman@linaro.org>

clockevents_config_and_register is superior compared to setting
shift/mult and {min,max}_delta_ns by hand.
Tested-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
[nsekhar@ti.com: fix an alignment related checkpatch warning]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

This augments the core machine code for the Integrator platforms
to get their references to the core module device nodes by
using compatible strings instead of predefined node names
and rename the CP syscon node to be simply "syscon".
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

In the PCIv3 driver, use devm_ioremap() instead of just ioremap()
when remapping the system controller in the PCIv3 driver, so
the mapping will be automatically released on probe failure.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This makes the Integrator cpufreq driver probe from the core
module device tree node through it's registered platforms
device, getting the memory base from the device tree,
remapping it and removing dependencies to <mach/platform.h>
and <mach/hardware.h> by moving the two affected CM
register offsets into the driver.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This moves the core module (CM) control base into the device
tree. It is a simple memory range of 0x200 bytes. Move the
cm header down into the machine directory and unexport the
cm_control() symbol as no modules are using it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This header is no longer needed when we boot from the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The Device Tree boot path now supports everything the ATAG
boot can provide, and the two are equivalent. This deletes
the ATAG boot path from the Integrator/AP and
Integrator/CP platforms to move them on to the future.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The static HW irqs have no meaning in the interrupt handler
and does not correlate to the /proc/interrupts IRQ numbers
anymore, print the Linux IRQ number instead.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The OF/DT boot path needs to get the LM (Logical Module)
IRQs from the device tree for coherency. This augments the
DT syscon node to contain these IRQs and alter the DT LM
code to get them from there.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

This updates the integrator defconfig, apart from the usual
re-shuffling of symbols due to restructuring of the kernel Kconfig
this will also:

- Enable IM-PD1 so all hardware is enabled out-of-the-box
- Enable the LEDs class and heartbeat trigger, so that the
  LED driver in plat-versatile/ is compiled.
- Enale some debug code like the CLK debug.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

The CM_CTRL register was accessed directly from the LED driver,
which does not work now that we get the base for the register
from the device tree. Add an accessor function to do this and
make the LED driver compile again.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge tag 'omap-for-v3.13/soc-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

From Tony Lindgren:
SoC related changes for omaps to support the realtime
counter on newer omaps, and to fail early for omap5 es1.0
SoCs that don't have any support merged for them in the
mainline tree.

* tag 'omap-for-v3.13/soc-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Fix build error for realtime counter init if not enabled
  ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register
  ARM: OMAP5: id: Remove ES1.0 support
  ARM: OMAP2+: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency
Signed-off-by: Kevin Hilman <khilman@linaro.org>

Merge tag 'omap-for-v3.13/hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

From Tony Lindgren:
omap hwmod related changes via Paul Walmsley <paul@pwsan.com>:

Some OMAP hwmod changes for 3.13.  Significant changes here include:

- support for moving some of the hwmod flags to DT data

- support for the SSI, hardware spinlock, USB host/TLL, and RNG IP
  blocks for various OMAPs

- a fix that again decouples hwmod data changes from unrelated DT data
  patchsets

Basic test logs are available at:

http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/20131009094936/

* tag 'omap-for-v3.13/hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP5: hwmod: add missing ocp2scp hwmod data
  ARM: AM33xx: hwmod: Add RNG module data
  ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT
  ARM: OMAP2+: hwmod: cleanup HWMOD_INIT_NO_RESET usage
  ARM: AM33xx: hwmod_data: add the sysc configuration for spinlock
  ARM: OMAP5: hwmod data: Add spinlock data
  ARM: OMAP5: hwmod data: Add USB Host and TLL modules
  ARM: OMAP2+: hwmod data: Add SSI information
  ARM: OMAP2+: hwmod: check for module address space during init

initcalls need to have platform specific checks so they are not run in
multi-platform builds.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>

Otherwise we can get an error with some configs:

arch/arm/mach-omap2/timer.c:73: undefined reference to `omap_smc1'
Signed-off-by: Tony Lindgren <tony@atomide.com>

Add this hwmod data to allow USB3 to work in OMAP5 boards.
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
[tony@atomide.com: updated to apply against Paul's changes]
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Merge tag 'keystone-soc-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/soc

From Santosh Shilimkar:
SOC updates for Keystone II devices:

- Clock tree support
- Clock management support using PM core
- Keystone config update for EMDA with ack from Vinod
- Enable SPI and I2C drivers

* tag 'keystone-soc-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: (510 commits)
  ARM: keystone: Enable I2C and SPI bus support
  ARM: keystone: Select TI_EDMA to be able to enable SPI driver
  dma: Allow TI_EDMA selectable for ARCH_KEYSTONE
  ARM: dts: keystone: Add the SPI nodes
  ARM: dts: keystone: Add i2c device nodes
  ARM: keystone: add PM domain support for clock management
  ARM: keystone: Enable clock drivers
  ARM: dts: keystone: Add clock phandle to UART nodes
  ARM: dts: keystone: Add clock tree data to devicetree
  +Linux 3.12-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>

Merge tag 'for-v3.13/hwmod' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.13/hwmod

Some OMAP hwmod changes for 3.13.  Significant changes here include:

- support for moving some of the hwmod flags to DT data

- support for the SSI, hardware spinlock, USB host/TLL, and RNG IP
  blocks for various OMAPs

- a fix that again decouples hwmod data changes from unrelated DT data
  patchsets

Basic test logs are available at:

http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/20131009094936/

The summary reports that the 4460varsomom boots are failing, but this looks
incorrect - it's probably a bug in the validation scripts here.

Keystone I2C dnd SPI driver updates are already merged so lets
enable them in config.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Select the TI EDMA to be able to enable SPI driver on Keystone
SOCs. Keystone SOCs share the EDMA IP with other TI SOCs.

Note that EDMA support hasn't been added and tested yet for
Keystone SOC data(device tree), but building it, is harmless since
driver like SPI already takes care of supporting non-dma mode
in the absence of such data.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Allow the TI_EDMA to be built for ARCH_KEYSTONE which also supports
the EDMA IP.
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Keystone2 based SOCs supports 3 instances of SPI controllers. Add
the device nodes for them.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Keystone2 based SOCs supports 3 instances of i2c controllers. Add
the device nodes for them. The i2c0 child device AT24C1024 EEPROM node
is also added. When different board variants are added in future, it
can be moved to the supported boards from common SOC file.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Add runtime PM core support to Keystone SOCs by using the pm_clk
infrastructure of the PM core. Patch is based on Kevin's pm_domain
work on DaVinci SOCs.

Keystone SOC doesn't have depedency to enable clocks in early
in the boot and hence the clock and PM domain initialisation is done
at subsys_init() level.

Cc: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>

Merge tag 'renesas-soc2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

From Simon Horman:
Second Round of Renesas ARM based SoC updates for v3.13

* SMP support for r8a7791 SoC
* r8a7779_init_irq_extpin() for DT for r8a7779 and r8a7778 SoCs
* Add HPB-DMAC to r8a7779 and r8a7778 SoCs
* Add r7s72100 SoC
* Make use of ARCH timer workaround on r8a7791 SoC
* Add IRQC platform device support to r8a7791 SoC
* Add I2C clocks and aliases for the DT mode for r8a7790 SoC
* Add MAC platform device to r8a73a4 SoC

* tag 'renesas-soc2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7791 SMP support
  ARM: shmobile: r8a7779: split r8a7779_init_irq_extpin() for DT
  ARM: shmobile: r8a7778: split r8a7778_init_irq_extpin() for DT
  ARM: shmobile: r7s72100 SCIF support
  ARM: shmobile: Initial r7s72100 SoC support
  ARM: shmobile: r8a7791 Arch timer workaround
  ARM: shmobile: r8a7791 IRQC platform device support
  ARM: shmobile: Introduce r8a7791_add_standard_devices()
  ARM: shmobile: Break out R-Car Gen2 setup code
  ARM: shmobile: r8a73a4: add a clock alias for the DMAC in DT mode
  ARM: shmobile: r8a7790: add I2C clocks and aliases for the DT mode
  ARM: shmobile: r8a7779: add HPB-DMAC support
  ARM: shmobile: r8a7778: add HPB-DMAC support
  ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it
  ARM: shmobile: Remove #gpio-ranges-cells DT property
  gpio: rcar: Remove #gpio-range-cells DT property usage
  ARM: shmobile: armadillo: fixup ether pinctrl naming
  ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixup
  ARM: shmobile: update SDHI DT compatibility string to the <unit>-<soc> format
Signed-off-by: Kevin Hilman <khilman@linaro.org>

The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other non-DT guest
OS. This register must be set to the right value by the
secure rom code. Setting this register helps in propagating the right
frequency value across OSes.

More discussions and the reason for adding this in a non-DT
way can be seen from below.
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html

So configuring this secure register for all the cpus here.

Cc: Nishanth Menon <nm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Add RNG hwmod data for AM33xx SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Now that we have DT bindings to specify which devices should not
be reset and idled during init, make hwmod extract the information
(and store them in internal flags) from Device tree.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

For modules/IPs/hwmods which do not have
-1- sys->class->reset()
and
-2- hardreset lines
and
-3- No way to do an ocp reset (no sysc control)
the flag 'HWMOD_INIT_NO_RESET' is not much useful.

Cleanup all such instances across various hwmod data files.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Add the missing sysc configuration to the AM335 spinlock hwmod
data. This ensures that smart-idle is enabled whenever the module
is enabled by the driver.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Add the hwmod data for the spinlock IP in OMAP5 SoC.
This is needed to be able to enable the OMAP spinlock
support for OMAP5.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Add hwmod data for High Speed USB host and TLL modules

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

This patch adds Synchronous Serial Interface (SSI) hwmod support for
OMAP34xx SoCs.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

The hwmod init sequence involves initializing and idling all the
hwmods during bootup. If a module class has sysconfig, the init
sequence utilizes the module register base for performing any
sysc configuration.

The module address space is being removed from hwmod database and
retrieved from the <reg> property of the corresponding DT node.
If a hwmod does not have its corresponding DT node defined and the
memory address space is not defined in the corresponding
omap_hwmod_ocp_if, then the module register target address space
would be NULL and any sysc programming would result in a NULL
pointer dereference and a kernel boot hang.

Handle this scenario by checking for a valid module address space
during the _init of each hwmod, and leaving it in the registered
state if no module register address base is defined in either of
the hwmod data or the DT data.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
[paul@pwsan.com: use -ENXIO rather than -ENOMEM to indicate a missing address
 space error; fixed checkpatch.pl problem]
Signed-off-by: Paul Walmsley <paul@pwsan.com>

OMAP5 ES1.0 was intended as a test chip and has major register level
differences w.r.t ES2.0 revision of the chip. All register defines,
dts support has been solely added for ES2.0 version of the chip.
Further, all ES1.0 chips and platforms are supposed to have been
removed from circulation. Hence, there is no need to further retain
any resemblence of ES1.0 support in id detection code.

Remove the omap_revision handling and BUG() instead to prevent folks
who mistakenly try an older unsupported chip and report bogus errors.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.

The ratio registers are missing for a sys-clk of 20MHZ which is used
by DRA7 socs. So because of this, the counter was getting wrongly
programmed for a sys-clk of 38.4Mhz(default). So adding the ratio
registers for 20MHZ sys-clk.
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>