- 08 Jan, 2014 7 commits
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Andrzej Hajda authored
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Acked-by:
Mike Turquette <mturquette@linaro.org> Acked-by:
Kukjin Kim <kgene.kim@samsung.com> Signed-off-by:
Tomasz Figa <t.figa@samsung.com>
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Andrzej Hajda authored
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by:
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Andrzej Hajda authored
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by:
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Andrzej Hajda authored
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by:
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Andrzej Hajda authored
The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by:
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Andrzej Hajda authored
The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by:
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Andrew Bresticker authored
Register the APLL rate table so that we can set the APLL rate from the cpufreq driver. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
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- 30 Dec, 2013 16 commits
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Sachin Kamat authored
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the clock rate in the cpufreq driver. Signed-off-by:
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Tomasz Figa authored
This patch adds mout_aclk333_sub mux clock and updates gate clocks from MFC domain to have it as their parent as specified in SoC documentation. Signed-off-by:
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Tomasz Figa authored
According to SoC documentation, input 5 of mout_audio muxes is connected to xxti (named fin_pll in the driver). This patch corrects defined parent arrays to match SoC documentation. Signed-off-by:
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Tomasz Figa authored
This patch updates mux parent arrays with unpopulated mux inputs, as all inputs need to be specified in parent arrays passed to clk_register_mux(), otherwise clk_set_parent() can generate out of bound accesses to the array. Signed-off-by:
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Tomasz Figa authored
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC documentation is the correct parent of DISP1 gate clocks. Signed-off-by:
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Tomasz Figa authored
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions of GSCL domain gate clocks to use it as their parent, as specified in SoC documentation. Signed-off-by:
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Tomasz Figa authored
This patch renames all mux clocks to start with mout_ prefix and all div clocks to start with div_ prefix for consistency with other clocks already defined this way. Signed-off-by:
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Tomasz Figa authored
This patch reorders clock definitions, so they are sorted by register addresses and bitfield shifts. When at it, blank lines are added to separate definitions of clocks from different registers. Overall this should make the driver more readable and reduce the number of potential conflicts when adding new entries. Signed-off-by:
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Tomasz Figa authored
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Krzysztof Kozlowski authored
Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only by suspend and resume functions. This fixes the warning on CONFIG_PM_SLEEP=n: drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable] Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by:
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Abhilash Kesavan authored
The sysreg (system register) generates control signals for various blocks like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused clock at boot-up. This can lead to failures in operation of above blocks, because they can not be configured properly if this clock is disabled. Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Acked-by:
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Abhilash Kesavan authored
Due to incorrect clock specified in MDMA0 node, using MDMA0 controller could cause system failures, due to wrong clock being controlled. This patch fixes this by specifying correct clock. Signed-off-by:
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Abhilash Kesavan authored
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure that the clock is enabled when MDMA0 is used on systems on which firmware gates the clockby default. Signed-off-by:
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Abhilash Kesavan authored
The CLK_GATE_IP_ACP register offset is incorrectly listed making definition of g2d clock incorrect, which may lead to system failures when trying to use G2D on systems on which firmware gates this clock by default. Fix this and the register ordering as well. Signed-off-by:
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Andrew Bresticker authored
The gate clocks for the MFC sysmmus appear to be flipped, i.e. GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr. Fix this so that the MFC will start up. Signed-off-by:
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Seung-Woo Kim authored
The SRC_MFC register offset was incorrect, which could cause have caused wrong calculation of rate of sclk_mfc clock, that could in turn lead to incorrect operation of MFC. This patch corrects it. Signed-off-by:
Seung-Woo Kim <sw0312.kim@samsung.com> Acked-by:
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- 28 Dec, 2013 1 commit
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Mike Turquette authored
Populate ${DEBUGS_MOUNT_POINT}/clk if CONFIG_DEBUG_FS is set. This eliminates the extra (annoying) step of enabling the config option manually. Signed-off-by:
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- 26 Dec, 2013 1 commit
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Sachin Kamat authored
'break' after 'goto' is redundant. Remove it. Signed-off-by:
Jonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by:
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- 23 Dec, 2013 4 commits
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Boris BREZILLON authored
This patch adds support for accuracy retrieval on fixed clocks. It also adds a new dt property called 'clock-accuracy' to define the clock accuracy. This can be usefull for oscillator (RC, crystal, ...) definitions which are always given an accuracy characteristic. Signed-off-by:
Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by:
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Boris BREZILLON authored
The clock accuracy is expressed in ppb (parts per billion) and represents the possible clock drift. Say you have a clock (e.g. an oscillator) which provides a fixed clock of 20MHz with an accuracy of +- 20Hz. This accuracy expressed in ppb is 20Hz/20MHz = 1000 ppb (or 1 ppm). Clock users may need the clock accuracy information in order to choose the best clock (the one with the best accuracy) across several available clocks. This patch adds clk accuracy retrieval support for common clk framework by means of a new function called clk_get_accuracy. This function returns the given clock accuracy expressed in ppb. In order to get the clock accuracy, this implementation adds one callback called recalc_accuracy to the clk_ops structure. This callback is given the parent clock accuracy (if the clock is not a root clock) and should recalculate the given clock accuracy. This callback is optional and may be implemented if the clock is not a perfect clock (accuracy != 0 ppb). Signed-off-by:
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Sachin Kamat authored
'clk_si570_of_match' is always compiled in. Hence the helper macro is not needed. Signed-off-by:
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Mike Turquette authored
Merge tag 'renesas-clock-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into clk-next-shmobile2 Renesas ARM based SoC Clock updates for v3.14 Add support for using emev2 SMU clocks with DT
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- 20 Dec, 2013 10 commits
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git://git.infradead.org/linux-mvebuMike Turquette authored
mvebu clock changes for v3.14 - mvebu: add the core divider clock driver - sparse cleanup
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git://git.xilinx.com/linux-xlnxMike Turquette authored
arm: Xilinx Zynq clk patches for v3.14 - Add support for fclk-enable feature
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Soren Brinkmann authored
In some use cases Zynq's FPGA clocks are used as static clock generators for IP in the FPGA part of the SOC for which no Linux driver exists and would control those clocks. To avoid automatic gating of these clocks in such cases a new property - fclk-enable - is added to the clock controller's DT description to accomodate such use cases. It's value is a bitmask, where a set bit results in enabling the corresponding FCLK through the clkc. FPGA clocks are handled following the rules below: If an FCLK is not enabled by bootloaders, that FCLK will be disabled in Linux. Drivers can enable and control it through the CCF as usual. If an FCLK is enabled by bootloaders AND the corresponding bit in the 'fclk-enable' DT property is set, that FCLK will be enabled by the clkc, resulting in an off by one reference count for that clock. Ensuring it will always be running. Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
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Sachin Kamat authored
Extra semicolon is redundant. Remove it. Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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Sachin Kamat authored
'vtwm_pll_ops' is local to this file. Make it static. Signed-off-by:
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Sachin Kamat authored
'of_cpu_clk_setup' is used only in this file. Make it static. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Sachin Kamat authored
clk_sp810_timerclken_of_get is used only in this file. Make it static. Signed-off-by:
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Sachin Kamat authored
'div_reg' is a pointer. Assign NULL instead of 0. Signed-off-by:
Dinh Nguyen <dinguyen@altera.com> Signed-off-by:
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Sachin Kamat authored
tegra_clk_periph_nodiv_ops is used only in this file. Make it static. Signed-off-by:
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Sachin Kamat authored
Local variables used only in this file are made static. Signed-off-by:
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- 19 Dec, 2013 1 commit
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Sachin Kamat authored
clk_frac_ops is local to this file. Make it static. Signed-off-by:
Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by:
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