- 28 Feb, 2018 16 commits
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Shirish S authored
The drm layer expects aux->transfer() to return the payload bytes read. Currently dm_dp_aux_transfer() returns the payload size which does not gets updated during the read, hence not giving the right data for the drm layer to pars edid. This leads to the drm layer to conclude as the edid is BAD and hence some monitors/devices dont get detected properly. This patch changes the return type of dm_dp_aux_transfer() to actual bytes read during DP_AUX_NATIVE_READ & DP_AUX_I2C_READ. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Monk Liu authored
otherwise there will be DMAR reading error comes out from CP since GFX is still alive and CPC's WPTR_POLL is still enabled, which would lead to DMAR read error. fix: we can hault CPG after hw_fini, but cannot halt CPC becaues KIQ stil need to be alive to let RLCV invoke, but its WPTR_POLL could be disabled. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
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Monk Liu authored
should use bo_create_kernel instead of split to two function that create and pin the SA bo issue: before this patch, there are DMAR read error in host side when running SRIOV test, the DMAR address dropped in the range of SA bo. fix: after this cleanups of SA init and fini, above DMAR eror gone. v2: keep sa_bo's fini instead of suspend, to keep reporting error Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Emily Deng authored
the original method will change the wptr value in wb. v2: furthur cleanup Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Monk Liu authored
issue: sometime GFX/MM ib test hit timeout under SRIOV env, root cause is that engine doesn't come back soon enough so the current IB test considered as timed out. fix: for SRIOV GFX IB test wait time need to be expanded a lot during SRIOV runtimei mode since it couldn't really begin before GFX engine come back. for SRIOV MM IB test it always need more time since MM scheduling is not go together with GFX engine, it is controled by h/w MM scheduler so no matter runtime or exclusive mode MM IB test always need more time. v2: use ring type instead of idx to judge Signed-off-by:
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Monk Liu authored
SRIOV doesn't give VF cg/pg feature so the MM's idle_work is skipped for SR-IOV v2: remove superfluous changes since idle_work is not scheduled for SR-IOV so the condition check for SR-IOV inside idle_work also can be dropped v3: drop the SRIOV check in amdgpu_vce/uvd_suspend Signed-off-by:
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Rex Zhu authored
Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Eric Huang authored
power containment disabled only on Fiji and compute power profile. It violates PCIe spec and may cause power supply failed. Enabling it will fix the issue, even the fix will drop performance of some compute tests. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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James Zhu authored
Emit frame size should match with corresponding function, uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Monk Liu authored
256MB is too small consider PTE/PDE shadow and TTM eviction activity Signed-off-by:
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Monk Liu authored
WB_FREE should be put after all engines's hw_fini done, otherwise the invalid wptr/rptr_addr would still be used by engines which trigger abnormal bugs. This fixes couple DMAR reading error in host side for SRIOV after guest kmd is unloaded. Signed-off-by:
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Monk Liu authored
two reasons to switch SCRATCH reg method to WB method: 1)Because when doing IB test we don't want to involve KIQ health status affect, and since SCRATCH register access is go through KIQ that way GFX IB test would failed due to KIQ fail. 2)acccessing SCRATCH register cost much more time than WB method because SCRATCH register access runs through KIQ which at least could begin after GPU world switch back to current Guest VF Signed-off-by:
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Monk Liu authored
issue: under SR-IOV sometimes the iB test will fail on gfx ring fix: with cond_exec inserted in RB the gfx engine would skip part packets if RLCV issue PREEMPT on gfx engine if gfx engine is prior to COND_EXEC packet, this is okay for regular command from UMD, but for the ib test since the whole dma format doesn't support PREEMPT so must remove the COND_EXEC from it. Signed-off-by:
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Monk Liu authored
since hotplug_work is initialized under the case of no dc support Signed-off-by:
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Monk Liu authored
Signed-off-by:
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Monk Liu authored
fix: should do right shift on wb before clearing cleanups: 1,should memset all wb buffer 2,set max wb number to 128 (total 4KB) is big enough Signed-off-by:
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- 27 Feb, 2018 24 commits
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Alex Deucher authored
For mclk od, use the vdd dependency on mclk table. Looks like a cut and paste typo. Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: -
Tom St Denis authored
DDR4 has a 64-bit width not 128-bits. It was reporting twice the width. Tested with my Ryzen 2400G. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Christian König authored
Cleanup ttm_tt_create a bit. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Christian König authored
Rename ttm_bo_add_ttm to ttm_tt_create and move it into ttm_tt.c. v2: separate the cleanup. Signed-off-by:
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Roger He authored
the free mem space and the lower limit both include two parts: system memory and swap space. For the OOM triggered by TTM, that is the case as below: first swap space is full of swapped out pages and soon system memory also is filled up with ttm pages. and then any memory allocation request will run into OOM. to cover two cases: a. if no swap disk at all or free swap space is under swap mem limit but available system mem is bigger than sys mem limit, allow TTM allocation; b. if the available system mem is less than sys mem limit but free swap space is bigger than swap mem limit, allow TTM allocation. v2: merge two memory limit(swap and system) into one v3: keep original behavior except ttm_opt_ctx->flags with TTM_OPT_FLAG_FORCE_ALLOC v4: always set force_alloc as tx->flags & TTM_OPT_FLAG_FORCE_ALLOC v5: add an attribute for lower_mem_limit v6: set lower_mem_limit as 0 to keep original behavior Signed-off-by: -
Christian König authored
Never used as parameter, the only driver actually using this is nouveau and there it is initialized after the BO is initialized. Signed-off-by:
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Christian König authored
Only used by the AGP backend and there it can be easily accessed using ttm->bdev->glob. Signed-off-by:
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Christian König authored
The pointer is available as ttm->bdev->glob as well. Signed-off-by:
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Christian König authored
The pointer is available as bo->bdev->glob as well. Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
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Christian König authored
TTM calls the default implementation now. Signed-off-by:
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Christian König authored
Use ttm_pool_populate/ttm_pool_unpopulate if the driver doesn't provide a function. Signed-off-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
1. move display num initialize out of dpm enable tasks. 2. do not set/restore smc telemetry if dpm is runing. Reviewed-by:
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Rex Zhu authored
Add dpm check functions on CZ/Vega10 to smu backend function table. Reviewed-by:
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Rex Zhu authored
when smu failed, print out the error info immediately for debug. smum_send_msg_to_smu always return true, so no need to check return value. Reviewed-by:
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Rex Zhu authored
When smu msssage failed, print out return value in dmesg. Reviewed-by:
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Rex Zhu authored
Avoid conflicts in reading the same register mmPCIE_INDEX2 with other clients Reviewed-by:
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