- 14 Dec, 2017 33 commits
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Tony Cheng authored
This prevents an issue where the MPCC will not go to idle due to us not waiting for it to become idle during disable plane. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andrew Jiang authored
- Only update DPP clock if it's a full update. - Program viewport on position change. This caused SLS regressions. Signed-off-by:
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Yongqiang Sun authored
When programming cursor position after front end programmed, if position is already set previously, it doesn't make sense to program position with all 0. Cache position and use the parameter after front end programming. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Yongqiang Sun authored
Cursor is abnormal after pipe_ctx is changed in context. Cause: cursor attributes is programmed right after front end programming, but it use old pipe_ctx to program which is not updated yet. Solution: Program cursor regs after context swapped. Signed-off-by:
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Yongqiang Sun authored
Fixed fliped landscape and fliped portrait hard hang. Signed-off-by:
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Eric Murphy-Zaremba authored
Signed-off-by:
Eric Murphy-Zaremba <Eric.Murphy-zaremba@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Eric Bernstein authored
Create opp_set_test_pattern function with similar interface and implementation as timing generator test pattern. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Vitaly Prosyak authored
Add color module to diagnostic compilation Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Eric Bernstein authored
During HW initialization, instead of assuming or detecting the existing MPCC mux configuration and then removing existing planes, reset all the MPCC muxes. Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Yongqiang Sun authored
HDR display playing video underflow is observed when switching to full screen due to program a lower watermark right after unlock otg. Instead of disable plane in next flip coming, if there is a plane disconnected, after otg unlock wait for mpcc idle and disable the plane, then program watermark. So there is enough warter mark to make sure current frame data pass through. Signed-off-by:
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Tony Cheng authored
Signed-off-by:
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Harry Wentland authored
Signed-off-by:
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Harry Wentland authored
Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:357 convert_to_custom_float() error: buffer overflow 'arr_points' 2 <= 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:358 convert_to_custom_float() warn: buffer overflow 'arr_points' 2 <= 2 Regression: drm/amd/display: Remove extra arr_points element Signed-off-by:
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Tony Cheng authored
Signed-off-by:
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Andrew Jiang authored
Program the DCC registers when dcc_change is true. Signed-off-by:
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Yongqiang Sun authored
Work around for a hw bug causing optc underflow if blank data double buffer disable and remove mpcc. Checking optc status after otg unlock, after wait mpcc idle check status again, if optc underflow just happens after wait mpcc idle, clear underflow status and enable blank data double buffer. Signed-off-by:
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Andrew Jiang authored
Rather than setting it every time there's a full update with surface count > 0, set it when we need to do plane_atomic_disconnect. Also make sure that we unset the flag in plane_atomic_disable, so that in the event we run through a sequence where we do disconnect followed by an immediate disable, we do not do unnecessarily request a passive flip to do the optimization. Signed-off-by:
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Harry Wentland authored
Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Signed-off-by:
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Yongqiang Sun authored
There is already wait mpcc idle function. It is better to use the same function for all wait mpcc idle. Signed-off-by:
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Eric Bernstein authored
Fix update_mpcc logic to only call assert_mpcc_idle_before_connect if mpcc is not already being used (and required removal). Update set_out_rate_control to include optional flow control parameter. In init_mpcc_from_hw check for case where bot_sel is same as mpcc_id. Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
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Harry Wentland authored
Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_ctx' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_vbios' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_ip' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_soc' Signed-off-by:
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Harry Wentland authored
pipe_ctx->stream and pipe_ctx->plane_state are never NULL Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2111 set_default_colors() error: we previously assumed 'pipe_ctx->stream' could be null (see line 2101) Signed-off-by:
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Harry Wentland authored
plane_res.mi (memory interface) can never be NULL for DCE110 Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2881 dce110_apply_ctx_for_surface() error: we previously assumed 'pipe_ctx->plane_res.mi' could be null (see line 2873) Signed-off-by:
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Harry Wentland authored
NULL check issue found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:1976 dc_link_setup_psr() warn: variable dereferenced before check 'link' (see line 1970) We don't use these functions so might as well remove them. Signed-off-by:
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Eric Bernstein authored
Integrating MPC pseudocode to support new blending cases with secondary MPCC list. This includes a design change to MPC data structures and interfaces. Signed-off-by:
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Tony Cheng authored
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Charlene Liu authored
[Description] in eDP+ HDMI/DP clone or extended configuration, audio inst changed from inst 1 to inst0. No failure related this though, just playback device endpoint inst changed. Also remove one addition register read. Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Yongqiang Sun authored
Before power gate plane, mpcc idle wait is processed, no need to wait another time. Signed-off-by:
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Rex Zhu authored
Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Roger He authored
Signed-off-by:
Roger He <Hongbo.He@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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- 13 Dec, 2017 7 commits
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Rex Zhu authored
RV implementation was missing these callbacks. Used to fetch the clock values for other components. Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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Alex Deucher authored
No longer used. Reviewed-by:
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Alex Deucher authored
The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by:
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Alex Deucher authored
The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by:
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Alex Deucher authored
Leftover from bring up. Acked-by:
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Alex Deucher authored
The golden register arrays were empty so the function was effectively useless. Acked-by:
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