Commits · ccda42a4629aa6ea48b5343a131ba420d0fa5c8f · Kirill Smelkov / linux

23 Jul, 2020 7 commits

drm/amdgpu/powerplay: add some documentation about memory clock · ccda42a4

Alex Deucher authored Jul 16, 2020

We expose the actual memory controller clock rate in Linux,
not the effective memory clock of the DRAMs.  To translate
it, it follows the following formula:

Clock conversion (Mhz):
HBM: effective_memory_clock = memory_controller_clock * 1
G5:  effective_memory_clock = memory_controller_clock * 1
G6:  effective_memory_clock = memory_controller_clock * 2

DRAM data rate (MT/s):
HBM: effective_memory_clock * 2 = data_rate
G5:  effective_memory_clock * 4 = data_rate
G6:  effective_memory_clock * 8 = data_rate

Bandwidth (MB/s):
data_rate * vram_bit_width / 8 = memory_bandwidth

Some examples:
G5 on RX460:
memory_controller_clock = 1750 Mhz
effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
data rate = 1750 * 4 = 7000 MT/s
memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s

G6 on RX5600:
memory_controller_clock = 900 Mhz
effective_memory_clock = 900 Mhz * 2 = 1800 Mhz
data rate = 1800 * 8 = 14400 MT/s
memory_bandwidth = 14400 * 192 bits / 8 = 345600 MB/s
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

ccda42a4

drm/amdgpu: Remove redundant NULL check · cc0e7ff8

Li Heng authored Jul 23, 2020

Fix below warnings reported by coccicheck:
./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:557:2-7: WARNING: NULL check before some freeing functions is not needed.

Fixes: 4d55b0dd ("drm/amd/display: Add DCN3 CLK_MGR")
Signed-off-by: Li Heng <liheng40@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

cc0e7ff8

drm/amdgpu: move umc specific macros to header · c5a4ef3e

John Clements authored Jul 23, 2020

certain umc macros are common across umc versions
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

c5a4ef3e

drm/amdgpu: update golden setting for sienna_cichlid · 8f3b800a

Likun Gao authored Jul 23, 2020

Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8f3b800a

drm/amd/powerplay: correct smu message for vf mode · 91190db1

Likun Gao authored Jul 21, 2020

Set valid_in_vf to false for the message not support in vf mode on
sienna cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

91190db1

drm/amd/powerplay: add msg map for mode1 reset · 7a3ecc82

Likun Gao authored Jul 21, 2020

Mapping Mode1Reset message for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

7a3ecc82

drm/amd/powerplay: skip invalid msg when smu set mp1 state · ebee9621

Likun Gao authored Jul 21, 2020

Some asic may not support for some message of set mp1 state.
If the return value of smu_send_smc_msg is -EINVAL, that means it failed
to send msg to smc as it can not map an valid message for the ASIC. And
with that case, smu_set_mp1_state should be skipped as those ASIC was in
fact do not support for that.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

ebee9621

22 Jul, 2020 12 commits

drm/amdgpu/dc: Simplify drm_crtc_state::active checks · 2afda735

Michel Dänzer authored Jul 22, 2020

drm_atomic_crtc_check enforces that ::active can only be true if
::enable is as well.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2afda735

drm/amd/powerplay: remove the dpm checking in the boot sequence · 8fe384ff

Kenneth Feng authored Jul 22, 2020

It's not necessary to retrieve the power features status when the
asic is booted up the first time. This patch can have the features
enablement status still checked in suspend/resume case and removed
from the first boot up sequence.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8fe384ff

drm/amd/amdgpu: Fix compiler warning in df driver · 06b668c1

Tom St Denis authored Jul 22, 2020

Fix this warning:

  CC [M]  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h:29,
                 from drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h:26,
                 from drivers/gpu/drm/amd/amdgpu/amdgpu.h:43,
                 from drivers/gpu/drm/amd/amdgpu/df_v3_6.c:23:
drivers/gpu/drm/amd/amdgpu/df_v3_6.c: In function ‘df_v3_6_pmc_get_count’:
./include/drm/drm_print.h:487:2: warning: ‘hi_base_addr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  487 |  __drm_dbg(DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
      |  ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:649:25: note: ‘hi_base_addr’ was declared here
  649 |  uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
      |                         ^~~~~~~~~~~~
In file included from drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h:29,
                 from drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h:26,
                 from drivers/gpu/drm/amd/amdgpu/amdgpu.h:43,
                 from drivers/gpu/drm/amd/amdgpu/df_v3_6.c:23:
./include/drm/drm_print.h:487:2: warning: ‘lo_base_addr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  487 |  __drm_dbg(DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
      |  ^~~~~~~~~
drivers/gpu/drm/amd/amdgpu/df_v3_6.c:649:11: note: ‘lo_base_addr’ was declared here
  649 |  uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0;
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>