- 21 Jun, 2024 20 commits
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Martin Hundebøll authored
The m_can driver sets and clears the CCCR.INIT bit during probe (both when testing the NON-ISO bit, and when configuring the chip). After clearing the CCCR.INIT bit, the transceiver enters normal mode, where it affects the CAN bus (i.e. it ACKs frames). This can cause troubles when the m_can node is only used for monitoring the bus, as one cannot setup listen-only mode before the device is probed. Rework the probe flow, so that the CCCR.INIT bit is only cleared when upping the device. First, the tcan4x5x driver is changed to stay in standby mode during/after probe. This in turn requires changes when setting bits in the CCCR register, as its CSR and CSA bits are always high in standby mode. Signed-off-by:
Martin Hundebøll <martin@geanix.com> Reviewed-by:
Markus Schneider-Pargmann <msp@baylibre.com> Tested-by:
Marc Kleine-Budde <mkl@pengutronix.de>
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Marc Kleine-Budde authored
Simplify SPI driver by making use of spi_get_device_match_data(). Link: https://lore.kernel.org/all/20240606142424.129709-1-krzysztof.kozlowski@linaro.org [mkl: add intermediate cast to uintptr_t] Signed-off-by:
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Krzysztof Kozlowski authored
Use spi_get_device_match_data() helper to simplify a bit the driver. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/all/20240606142424.129709-3-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Use spi_get_device_match_data() helper to simplify a bit the driver. Signed-off-by:
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Krzysztof Kozlowski authored
Use spi_get_device_match_data() helper to simplify a bit the driver. Signed-off-by:
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Marc Kleine-Budde authored
Martin Jocic <martin.jocic@kvaser.com> says: This patch series adds support for MSI interrupts. It depends on the patch series can: kvaser_pciefd: Minor improvements and cleanups. Link: https://lore.kernel.org/all/20240620181320.235465-1-martin.jocic@kvaser.comSigned-off-by:
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Martin Jocic authored
Use MSI interrupts with fallback to INTx interrupts. Signed-off-by:
Martin Jocic <martin.jocic@kvaser.com> Link: https://lore.kernel.org/all/20240620181320.235465-3-martin.jocic@kvaser.com [mkl: kvaser_pciefd_probe(): call pci_free_irq_vectors() unconditionally] Signed-off-by:
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Martin Jocic authored
A new interrupt is triggered by resetting the DMA RX buffers. Since MSI interrupts are faster than legacy interrupts, the reset of the DMA buffers must be moved to the very end of the ISR, otherwise a new MSI interrupt will be masked by the current one. Signed-off-by:
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Marc Kleine-Budde authored
Martin Jocic <martin.jocic@kvaser.com> says: Minor improvements and cleanups for the kvaser_pciefd driver in preparation for an upcoming MSI interrupts patch series. Link: https://lore.kernel.org/all/20240614151524.2718287-1-martin.jocic@kvaser.comSigned-off-by:
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Martin Jocic authored
Replace the variable name err used for return codes with the more generic name ret. An upcoming patch series for adding MSI interrupts will introduce code which also returns values other than return codes. Renaming the variable to ret enables using it for both purposes. This is applied to the whole file to make it consistent. Signed-off-by:
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Martin Jocic authored
Rename the variable name board_irq in the ISR to pci_irq to be more specific and to match the macro by which it is read. Signed-off-by:
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Martin Jocic authored
Use unlikely for some unexpected errors. Signed-off-by:
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Martin Jocic authored
Make the short function kvaser_pciefd_set_tx_irq inline. This function is effectively three lines long and therefore inlining it should be OK according to rule #15 of the Linux kernel coding style. Signed-off-by:
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Martin Jocic authored
The code speaks for itself. Signed-off-by:
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Martin Jocic authored
This check is already done at the creation of the net devices in kvaser_pciefd_setup_can_ctrls called from kvaser_pciefd_probe. If it fails, the driver won't load, so there should be no need to repeat the check inside the ISR. The number of channels is read from the FPGA and should be trusted. Signed-off-by:
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Martin Jocic authored
Increases readability Signed-off-by:
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Marc Kleine-Budde authored
Martin Jocic <martin.jocic@kvaser.com> says: This patch series adds support for the following devices: * Vining 800 * Kvaser USBcan Pro 5xCAN * Kvaser Mini PCIe 1xCAN Link: https://lore.kernel.org/all/20240612141946.3352364-1-martin.jocic@kvaser.comSigned-off-by:
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Martin Jocic authored
Add support for Kvaser Mini PCIe 1xCAN, based on the hydra platform. Signed-off-by:
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Martin Jocic authored
Add support for Kvaser USBcan Pro 5xCAN, based on the hydra platform. Signed-off-by:
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Martin Jocic authored
Add support for Vining 800, a branded device based on the hydra platform. Signed-off-by:
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- 20 Jun, 2024 20 commits
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Dr. David Alan Gilbert authored
'mscan_state' is unused since the original commit afa17a50 ("net/can: add driver for mscan family & mpc52xx_mscan"). Remove it. Signed-off-by:
Dr. David Alan Gilbert <linux@treblig.org> Reviewed-by:
Simon Horman <horms@kernel.org> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/all/20240525232509.191735-1-linux@treblig.orgSigned-off-by:
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Marc Kleine-Budde authored
Francesco Valla <valla.francesco@gmail.com> says: While the in-kernel ISO 15765-2 (ISO-TP) stack is fully functional and easy to use, no documentation exists for it. This patch adds such documentation, containing the very basics of the protocol, the APIs and a basic example. Link: https://lore.kernel.org/all/20240501092413.414700-1-valla.francesco@gmail.comSigned-off-by:
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Francesco Valla authored
Document basic concepts, APIs and behaviour of the ISO 15675-2 (ISO-TP) CAN stack. Signed-off-by:
Francesco Valla <valla.francesco@gmail.com> Reviewed-by:
Bagas Sanjaya <bagasdotme@gmail.com> Reviewed-by:
Vincent Mailhol <mailhol.vincent@wanadoo.fr> Link: https://lore.kernel.org/all/20240501092413.414700-2-valla.francesco@gmail.comSigned-off-by:
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Marc Kleine-Budde authored
Harini T <harini.t@amd.com> says: Xilinx CAN driver supports AXI CAN, AXI CANFD, CANPS and CANFD PS IPs. 1. Modify the dt-bindings title to indicate that both controllers are supported. 2. Document all supported IPs in driver comment description. Link: https://lore.kernel.org/all/20240503060553.8520-1-harini.t@amd.comSigned-off-by:
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Harini T authored
Xilinx CAN driver supports AXI CAN, AXI CANFD, CANPS and CANFD PS IPs. Document all supported IPs in comment description. Signed-off-by:
Harini T <harini.t@amd.com> Link: https://lore.kernel.org/all/20240503060553.8520-3-harini.t@amd.comSigned-off-by:
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Oliver Hartkopp authored
With the new ISO 15765-2:2024 release the former documentation and comments have to be reworked. This patch removes the ISO specification version/date where possible. Signed-off-by:
Oliver Hartkopp <socketcan@hartkopp.net> Acked-by:
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Harini T authored
Xilinx CAN binding documentation supports CAN and CANFD controllers. Modify the title to indicate that both controllers are supported. Signed-off-by:
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Mans Rullgard authored
Commit cfcb4465 ("can: slcan: remove legacy infrastructure") removed the 10-device limit. Update the Kconfig help text accordingly. Signed-off-by:
Mans Rullgard <mans@mansr.com> Acked-by:
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Andy Shevchenko authored
There is predefined PCI_SUBVENDOR_ID_CONNECT_TECH, use it in the driver. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
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Andy Shevchenko authored
This driver is including the legacy GPIO header <linux/gpio.h> but the only thing it is using from that header is the wrong define for GPIOF_DIR_OUT. Fix it up by using GPIO_LINE_DIRECTION_* macros respectively. Signed-off-by:
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Jakub Kicinski authored
Shannon Nelson says: ==================== ionic: rework fix for doorbell miss A latency test in a scaled out setting (many VMs with many queues) has uncovered an issue with our missed doorbell fix from commit b69585bf ("ionic: missed doorbell workaround") As a refresher, the Elba ASIC has an issue where once in a blue moon it might miss/drop a queue doorbell notification from the driver. This can result in Tx timeouts and potential Rx buffer misses. The basic problem with the original solution is that we're delaying things with a timer for every single queue, periodically using mod_timer() to reset to reset the alarm, and mod_timer() becomes a more and more expensive thing as there are more and more VFs and queues each with their own timer. A ping-pong latency test tends to exacerbate the effect such that every napi is doing a mod_timer() in every cycle. An alternative has been worked out to replace this using periodic workqueue items outside the napi cycle to request a napi_schedule driven by a single delayed-workqueue per device rather than a timer for every queue. Also, now that newer firmware is actually reporting its ASIC type, we can restrict this to the appropriate chip. The testing scenario used 128 VFs in UP state, 16 queues per VF, and latency tests were done using TCP_RR with adaptive interrupt coalescing enabled, running on 1 VF. We would see 99th percentile latencies of up to 900us range, with some max fliers as much as 4ms. With these fixes the 99th percentile latencies are typically well under 50us with the occasional max under 500us. v1: https://lore.kernel.org/netdev/20240610230706.34883-1-shannon.nelson@amd.com/ ==================== Link: https://lore.kernel.org/r/20240619003257.6138-1-shannon.nelson@amd.comSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Brett Creeley authored
If the doorbell workaround isn't required for a certain asic_type then there is no need to run the associated code. Since newer FW versions are finally reporting their asic_type we can use a flag to determine whether or not to do the workaround. Signed-off-by:
Brett Creeley <brett.creeley@amd.com> Signed-off-by:
Shannon Nelson <shannon.nelson@amd.com> Link: https://lore.kernel.org/r/20240619003257.6138-9-shannon.nelson@amd.comSigned-off-by:
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Brett Creeley authored
We only support (u16)-1 size for rx_copybreak, so we can reduce the field size and move a couple other fields around to save a little space in the ionic_lif struct. Before: /* size: 17440, cachelines: 273, members: 56 */ /* sum members: 17403, holes: 9, sum holes: 37 */ /* last cacheline: 32 bytes */ After: /* size: 17424, cachelines: 273, members: 56 */ /* sum members: 17401, holes: 7, sum holes: 23 */ /* last cacheline: 16 bytes */ Signed-off-by:
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Shannon Nelson authored
Check the deadline against the last time run and only schedule a new napi if we haven't been run recently. Signed-off-by:
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Shannon Nelson authored
Add a work item for each queue that will be run on the queue's preferred cpu and will schedule another napi. This napi is run in case the device missed a doorbell and didn't process a packet. This is a problem for the Elba asic that happens very rarely. Signed-off-by:
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Shannon Nelson authored
Add the first queued work for checking on the missed doorbell. This is a delayed work item that reschedules itself every cycle starting at probe. Signed-off-by:
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Shannon Nelson authored
Instead of using the system's default workqueue, add a private workqueue for the device to use for its little jobs. This is to better support the new work items we will be adding in the next patches for PF and VF specific jobs, without inundating the system workqueue in a couple of customer cases where our devices get scaled out to 100-200 VFs. Signed-off-by:
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Brett Creeley authored
Currently the driver either sets the initial interrupt affinity for its adminq and tx/rx queues on probe or resets it on various down/up/reconfigure flows. If any user and/or user process (i.e. irqbalance) changes IRQ affinity for any of the driver's interrupts that will be reset to driver defaults whenever any down/up/reconfigure operation happens. This is incorrect and is fixed by making 2 changes: 1. Allocate an array of cpumasks that's only allocated on probe and destroyed on remove. 2. Update the cpumask(s) for interrupts that are in use by registering for affinity notifiers. Signed-off-by:
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Shannon Nelson authored
Remove the timer-per-queue mechanics from the missed doorbell check in preparation for the new missed doorbell fix. Signed-off-by:
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Jakub Kicinski authored
Petr Machata says: ==================== mlxsw: Use page pool for Rx buffers allocation Amit Cohen writes: After using NAPI to process events from hardware, the next step is to use page pool for Rx buffers allocation, which is also enhances performance. To simplify this change, first use page pool to allocate one continuous buffer for each packet, later memory consumption can be improved by using fragmented buffers. This set significantly enhances mlxsw driver performance, CPU can handle about 370% of the packets per second it previously handled. The next planned improvement is using XDP to optimize telemetry. Patch set overview: Patches #1-#2 are small preparations for page pool usage Patch #3 initializes page pool, but do not use it Patch #4 converts the driver to use page pool for buffers allocations Patch #5 is an optimization for buffer access Patch #6 cleans up an unused structure Patch #7 uses napi_consume_skb() as part of Tx completion ==================== Link: https://lore.kernel.org/r/cover.1718709196.git.petrm@nvidia.comSigned-off-by:
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