- 05 Dec, 2016 1 commit
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Daniel Vetter authored
Signed-off-by:Daniel Vetter <daniel.vetter@ffwll.ch>
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- 02 Dec, 2016 16 commits
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Rodrigo Vivi authored
According to Bspec we need to "Poll for PORT_REF_DW3_A grc_done == 1b" only on ports B and C initialization sequence when copying rcomp from port A. So let's follow the spec and only poll for that case and not on every port A initialization. v2: Also remove the grc_done check from bxt_ddi_phy_is_enabled() otherwise it might believe it is disabled and force it to re program. Cc: Imre Deak <imre.deak@intel.com> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by:Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1479410256-25735-1-git-send-email-rodrigo.vivi@intel.com
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Ander Conselvan de Oliveira authored
Geminilake has 4 planes (3 sprites) per pipe. Signed-off-by:
Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by:
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Ander Conselvan de Oliveira authored
The sequence is pretty much the same as broxton, except that bspec requires the AUX domains to be enabled. But since those can't be enabled before the phys are initialized, we just use the same sequence as broxton. v2: Don't manually enable AUX domains. (Ander) Signed-off-by:
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Ander Conselvan de Oliveira authored
Geminilake has double wide pipes so it can output two pixels per CD clock. Signed-off-by:
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Ander Conselvan de Oliveira authored
Geminilake has the same register layout, reference clock and programming sequence as broxton. The difference is that it doesn't support the 1.5 divider and has different ratios, but a lot of code can be shared between the two platforms. v2: Rebase (s/broxton/bxt). v3: Fix vco calculation in glk_de_pll_vco(). Signed-off-by:
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Madhav Chauhan authored
Add steps for enabling and disabling Port PLL as per bspec. Signed-off-by:
Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by:
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Ander Conselvan de Oliveira authored
Follow the PLL enable sequence updated in bspec, which requires the DCC delay range 2 bit to be set. v2: Moved from DDI init sequence to PLL enable. v3: Don't read value from GRP register. (Rodrido) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ander Conselvan de Oliveira authored
Implement the DDI initsequence and add information about the different phys in GLK. v2: Rebase on the move of phys to be power wells. v3: Rebase on addition of struct bxt_ddi_phy_info. Signed-off-by:
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Ander Conselvan de Oliveira authored
Geminilake has power wells are similar to SKL, but with the misc IO well being split into separate AUX IO wells. Signed-off-by:
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Ander Conselvan de Oliveira authored
Geminilake is mostly backwards compatible with broxton, so change most of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the platforms will be implemented in follow-up patches. v2: Don't reuse broxton's path in intel_update_max_cdclk(). Don't set plane count as in broxton. v3: Rebase v4: Include the check intel_bios_is_port_hpd_inverted(). Commit message. v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo) v6: Rebase. v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll code. (Rodrigo) v8: Squash a couple of DDI patches with more conversions. (Rodrigo) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: -
Imre Deak authored
The spec calls for the upper data byte to be cleared before most of the PCODE write commands, for others like IPS control it doesn't say anything about this byte. Let's clear it in case it's clobbered somehow, especially that there are places where we only do a PCODE write without a preceding PCODE read. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480346969-16121-1-git-send-email-imre.deak@intel.com
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Libin Yang authored
Remove the type judgement in i915_audio_component_sync_audio_rate(). Audio rate sync is necessary for all i915 digital audio now. Signed-off-by:
Libin Yang <libin.yang@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Libin Yang authored
In initialization, audio driver will call functions get_eld() and etc. But at that time, audio driver may not know whether it is DP MST or not. In the original function get_saved_enc(), if it is DP MST, it requires to set the pipe to the correct value, otherwise, pipe to be -1. Although audio driver can get the knowledge whether it is in DP MST mode or not by reading the codec register. It will drop performance each time before it calls the get_eld and other similar functions. As gfx driver can easily know whether it is in DP MST mode or not. Let's extend the get_saved_enc() function to handle the situation that audio driver still sends the device id info even it is in DP SST mode and return the correct intel_encoder instead of panic. Signed-off-by:
Libin Yang <libin.yang@linux.intel.com> Reviewed-by:
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Matthew Auld authored
Looks like this was missed when unexporting, so let's keep sparse happy. Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Fixes: 7f26cb88 ("drm/i915: Unexport VGA switcheroo functions") Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
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Tvrtko Ursulin authored
Recent refactoring forgot to update this one. Signed-off-by:
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Ander Conselvan de Oliveira authored
In commit c39055b0 ("drm/i915: Pass dev_priv to intel_setup_outputs()"), I forgot to update the kerneldoc for intel_psr_init() init, leading to warnings when building the documentation: drivers/gpu/drm/i915/intel_psr.c:822: warning: No description found for parameter 'dev_priv' drivers/gpu/drm/i915/intel_psr.c:822: warning: Excess function parameter 'dev' description in 'intel_psr_init' Fixes: c39055b0 ("drm/i915: Pass dev_priv to intel_setup_outputs()") Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Signed-off-by:
Daniel Vetter <daniel.vetter@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480420127-11382-1-git-send-email-ander.conselvan.de.oliveira@intel.com
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- 01 Dec, 2016 16 commits
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Tvrtko Ursulin authored
Function actually wants dev_priv so give it to it. v2: Commit message. (Joonas Lahtinen) Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480601805-14391-2-git-send-email-tvrtko.ursulin@linux.intel.com
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Tvrtko Ursulin authored
dev_priv is more appropriate since it is used much more in these. v2: Commit message and keep the local pdev variable. (Joonas Lahtinen) Signed-off-by:
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Tvrtko Ursulin authored
Since it does not need dev at all. Also change the stored pointer in struct i915_error_state_file_priv to i915. Signed-off-by:
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Tvrtko Ursulin authored
Simplify the code by passing the right argument in. v2: Commit message. (Joonas Lahtinen) Signed-off-by:
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Tvrtko Ursulin authored
They are only used in i915_drv.c so a forward declaration is enough. Signed-off-by:
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Tvrtko Ursulin authored
dev_priv is more appropriate for these so converting saves some lines of source. v2: Commit message and keep the pdev local variable. (Joonas Lahtinen) Signed-off-by:
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Tvrtko Ursulin authored
Simplifies the code to pass the right parameter in. v2: Commit message. (Joonas Lahtinen) Signed-off-by:
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Tvrtko Ursulin authored
Like GEM init, GUC init, MOCS init and context creation. Enables them to lose dev_priv locals. Signed-off-by:
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Tvrtko Ursulin authored
Makes all GEM object constructors consistent. v2: Fix compilation in GVT code. Signed-off-by:
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Tvrtko Ursulin authored
Where it is more appropriate and also to be consistent with the direction of the driver. v2: Leave out object alloc/free inlining. (Joonas Lahtinen) Signed-off-by:
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Imre Deak authored
For LSPCON initialization during system resume we need AUX functionality, but we call the corresponding encoder reset hook with all interrupts disabled. Without interrupts we'll do a poll-wait for AUX transfer completions, which adds a significant delay if the transfers timeout/need to be retried for some reason. Fix this by enabling interrupts before calling the reset hooks. Note that while this will enable AUX interrupts it will keep HPD interrupts disabled, in a similar way to the init time output setup code. This issue existed since LSPCON support was added. v2: - Rebased on drm-tip. Cc: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by:
David Weinehall <david.weinehall@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1480448429-27739-1-git-send-email-imre.deak@intel.com
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Ander Conselvan de Oliveira authored
Broxton and Geminilake are both gen9lp platforms. To avoid adding IS_GEMINILAKE() checks everywhere alongside the IS_BROXTON() ones, add a IS_GEN9_LP() macro. v2: Rename macro parameter to dev_priv. (Joonas) Signed-off-by:
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Ander Conselvan de Oliveira authored
v2: Add new 0x3185 ID. (Joonas) Signed-off-by:
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Ander Conselvan de Oliveira authored
Geminilake is an Intel
® Processor containing Intel® HD Graphics following Broxton. Let's start by adding the platform definition. PCI IDs and plaform specific code will follow. v2: Rebase (don't allow dev to be used with the new macro). v3: Update ddb size. (Matt) Rebase on s/preliminary_hw/alpha/ Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: -
Rodrigo Vivi authored
The following LP platform inherits a lot of this platform So let's simplify here to re-use this later. v2: Keep ddb_size out of the new macro. v3: Rebase (has_decoupled_mmio). (Imre) Signed-off-by:
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Chris Wilson authored
Forgo marking up the u64 integer representing a user pointer as this just annoys sparse. The conversion from u64 to a user pointer is managed by u64_to_user_ptr(). Fixes: eec688e1 ("drm/i915: Add i915 perf infrastructure") Signed-off-by:
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- 30 Nov, 2016 1 commit
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Daniel Vetter authored
Since commit 44adece5 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Aug 10 18:52:34 2016 +0200 drm/fb-helper: Add a dummy remove_conflicting_framebuffers the drm helpers take care of this for us. Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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- 29 Nov, 2016 6 commits
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Ville Syrjälä authored
Looks like we're only initializing dev_priv->atomic_cdclk_freq at resume and commit times, not at init time. Let's do that as well. We're now hitting the 'WARN_ON(intel_state->cdclk == 0)' in hsw_compute_linetime_wm() on account of populating intel_state->cdclk from dev_priv->atomic_cdclk_freq. Previously we were mispopulating intel_state->cdclk with dev_priv->cdclk_freq which always had a proper value at init time and hence the WARN_ON() didn't trigger. Cc: stable@vger.kernel.org Cc: Matthew Auld <matthew.auld@intel.com> Reported-by:
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Chris Wilson authored
Something I missed before sending off the partial series was that the non-scheduler guc reset path was broken (in the full series, this is pushed to the execlists reset handler). The issue is that after a reset, we have to refill the GuC workqueues, which we do by resubmitting the requests. However, if we already have submitted them, the fences within them have already been used and triggering them again is an error. Instead, just repopulate the guc workqueue. [ 115.858560] [IGT] gem_busy: starting subtest hang-render [ 135.839867] [drm] GPU HANG: ecode 9:0:0xe757fefe, in gem_busy [1716], reason: Hang on render ring, action: reset [ 135.839902] drm/i915: Resetting chip after gpu hang [ 135.839957] [drm] RC6 on [ 135.858351] ------------[ cut here ]------------ [ 135.858357] WARNING: CPU: 2 PID: 45 at drivers/gpu/drm/i915/i915_sw_fence.c:108 i915_sw_fence_complete+0x25/0x30 [ 135.858357] Modules linked in: rfcomm bnep binfmt_misc nls_iso8859_1 input_leds snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic snd_hda_intel snd_hda_codec snd_hda_core btusb btrtl snd_hwdep snd_pcm 8250_dw snd_seq_midi hid_lenovo snd_seq_midi_event snd_rawmidi iwlwifi x86_pkg_temp_thermal coretemp snd_seq crct10dif_pclmul snd_seq_device hci_uart snd_timer crc32_pclmul ghash_clmulni_intel idma64 aesni_intel virt_dma btbcm snd btqca aes_x86_64 btintel lrw cfg80211 bluetooth gf128mul glue_helper ablk_helper cryptd soundcore intel_lpss_pci intel_pch_thermal intel_lpss_acpi intel_lpss acpi_als mfd_core kfifo_buf acpi_pad industrialio autofs4 hid_plantronics usbhid dm_mirror dm_region_hash dm_log sdhci_pci ahci sdhci libahci i2c_hid hid [ 135.858389] CPU: 2 PID: 45 Comm: kworker/2:1 Tainted: G W 4.9.0-rc4+ #238 [ 135.858389] Hardware name: /NUC6i3SYB, BIOS SYSKLi35.86A.0024.2015.1027.2142 10/27/2015 [ 135.858392] Workqueue: events_long i915_hangcheck_elapsed [ 135.858394] ffffc900001bf9b8 ffffffff812bb238 0000000000000000 0000000000000000 [ 135.858396] ffffc900001bf9f8 ffffffff8104f621 0000006c00000000 ffff8808296137f8 [ 135.858398] 0000000000000a00 ffff8808457a0000 ffff880845764e60 ffff880845760000 [ 135.858399] Call Trace: [ 135.858403] [<ffffffff812bb238>] dump_stack+0x4d/0x65 [ 135.858405] [<ffffffff8104f621>] __warn+0xc1/0xe0 [ 135.858406] [<ffffffff8104f748>] warn_slowpath_null+0x18/0x20 [ 135.858408] [<ffffffff813f8c15>] i915_sw_fence_complete+0x25/0x30 [ 135.858410] [<ffffffff813f8fad>] i915_sw_fence_commit+0xd/0x30 [ 135.858412] [<ffffffff8142e591>] __i915_gem_request_submit+0xe1/0xf0 [ 135.858413] [<ffffffff8142e5c8>] i915_gem_request_submit+0x28/0x40 [ 135.858415] [<ffffffff814433e7>] i915_guc_submit+0x47/0x210 [ 135.858417] [<ffffffff81443e98>] i915_guc_submission_enable+0x468/0x540 [ 135.858419] [<ffffffff81442495>] intel_guc_setup+0x715/0x810 [ 135.858421] [<ffffffff8142b6b4>] i915_gem_init_hw+0x114/0x2a0 [ 135.858423] [<ffffffff813eeaa8>] i915_reset+0xe8/0x120 [ 135.858424] [<ffffffff813f3937>] i915_reset_and_wakeup+0x157/0x180 [ 135.858426] [<ffffffff813f79db>] i915_handle_error+0x1ab/0x230 [ 135.858428] [<ffffffff812c760d>] ? scnprintf+0x4d/0x90 [ 135.858430] [<ffffffff81435985>] i915_hangcheck_elapsed+0x275/0x3d0 [ 135.858432] [<ffffffff810668cf>] process_one_work+0x12f/0x410 [ 135.858433] [<ffffffff81066bf3>] worker_thread+0x43/0x4d0 [ 135.858435] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410 [ 135.858436] [<ffffffff81066bb0>] ? process_one_work+0x410/0x410 [ 135.858438] [<ffffffff8106bbb4>] kthread+0xd4/0xf0 [ 135.858440] [<ffffffff8106bae0>] ? kthread_park+0x60/0x60 v2: Only resubmit submitted requests v3: Don't forget the pending requests have reserved space. Fixes: d55ac5bf ("drm/i915: Defer transfer onto execution timeline to actual hw submission") Signed-off-by:
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Chris Wilson authored
In order to avoid some complexity in trying to reconstruct the workqueues across reset, remember them instead. The issue comes when we have to handle a reset between request allocation and submission, the request has reserved space in the wq, but is not in any list so we fail to restore the reserved space. By keeping the execbuf client intact across the reset, we also keep the reservations. Signed-off-by:
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Chris Wilson authored
Set the initial value of the doorbell cookie from the client. Signed-off-by:
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Chris Wilson authored
The client->cookie is a shadow of the doorbell->cookie value, so rename it to indicate its association with the doorbell, like the doorbell id and offset. Signed-off-by:
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Chris Wilson authored
i915_guc_info() (part of debugfs output) tries to avoid holding struct_mutex for a long period by copying onto the stack. This causes a warning that the stack frame is massive, so stop doing that. We can even forgo holding the struct_mutex here as that doesn't serialise the values being read (and the lists used exist for the device lifetime). v2: Skip printing anything if guc->execbuf_client is disabled (avoids potential NULL dereference). Signed-off-by:
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