- 15 Mar, 2011 9 commits
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Xulei authored
Update p1022 sata compatible to "fsl,p1022-sata", "fsl,pq-sata-v2". p1022ds sata controller is v2 version comparing previous FSL sata controller, for example, mpc8536. Signed-off-by:
Lei Xu <B33228@freescale.com> Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Xulei authored
In FSL sata v2 block, the snoop bit of PRDT Word3 description information is at bit28 instead of bit22. This patch adds FSL sata v2 probe and resolve this difference. Signed-off-by:
Jeff Garzik <jgarzik@redhat.com> Signed-off-by:
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Anatolij Gustschin authored
Commit da3ed89e added 'fsl,qoriq-gpio' compatiable searching in the old way using for_each_compatible_node(). But the driver have previously been changed to use a struct of_device_id compatible list passed to for_each_matching_node(). Add 'fsl,qoriq-gpio' compatiable to the existing compatible list instead of adding another for_each_compatible_node() loop. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
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Holger Brunck authored
The MPC852 based mgsuvd board from Keymile was initially ported, but later on not developed further. This patch removes the respective files to decrease merging conflicts and unneeded maintenance. Signed-off-by:
Holger Brunck <holger.brunck@keymile.com> Acked-by: Heiko Schocher<hs@denx.de> Cc: Vitaly Bordug <vitb@kernel.crashing.org> Cc: Marcelo Tosatti <marcelo@kvack.org> Signed-off-by:
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Holger Brunck authored
The mgcoge board from keymile is now base for some other similar boards. Therefore the board specific name mgcoge was renamed to a generic name km82xx. Additionally some enhancements were made: - rework partition table in dts file - add cpm2_pio_c gpio controller in dts file - update defconfig - add pin description for SCC1 - add pin description and configuration for USB Signed-off-by:
Heiko Schocher <hs@denx.de> CC: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: Heiko Schocher <hs@denx.de> Signed-off-by:
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Holger Brunck authored
Beside the MPC 8360 based board kmeter1 other km83xx boards from keymile will follow. Therefore the board specific naming kmeter1 for functions and files were replaced with km83xx. Additionally some updates were made: - update defconfig for 2.6.38 - rework flash partitioning in dts file - add gpio controller for qe_pio_c in dts Signed-off-by: -
Liu Yu authored
This erratum can occur if a single-precision floating-point, double-precision floating-point or vector floating-point instruction on a mispredicted branch path signals one of the floating-point data interrupts which are enabled by the SPEFSCR (FINVE, FDBZE, FUNFE or FOVFE bits). This interrupt must be recorded in a one-cycle window when the misprediction is resolved. If this extremely rare event should occur, the result could be: The SPE Data Exception from the mispredicted path may be reported erroneously if a single-precision floating-point, double-precision floating-point or vector floating-point instruction is the second instruction on the correct branch path. According to errata description, some efp instructions which are not supposed to trigger SPE exceptions can trigger the exceptions in this case. However, as we haven't emulated these instructions here, a signal will send to userspace, and userspace application would exit. This patch re-issue the efp instruction that we haven't emulated, so that hardware can properly execute it again if this case happen. Signed-off-by:
Liu Yu <yu.liu@freescale.com> Signed-off-by:
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Prabhakar Kushwaha authored
FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new config and interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. Device tree is used to maintain backward compatibility i.e. update inbound window 1 index depending upon "compatible" field witin PCIE node. Signed-off-by:Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by:
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Kumar Gala authored
If the spin table is located in the linear mapping (which can happen if we have 4G or more of memory) we need to access the spin table via a cacheable coherent mapping like we do on ppc32 (and do explicit cache flush). See the following commit for the ppc32 version of this issue: commit d1d47ec6 Author: Peter Tyser <ptyser@xes-inc.com> Date: Fri Dec 18 16:50:37 2009 -0600 powerpc/85xx: Fix SMP when "cpu-release-addr" is in lowmem Signed-off-by:
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- 11 Mar, 2011 1 commit
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Nishanth Aravamudan authored
On upcoming hardware, we have a PCI adapter with two functions, one of which uses MSI and the other uses MSI-X. This adapter, when MSI is disabled using the "old" firmware interface (RTAS_CHANGE_FN), still signals an MSI-X interrupt and triggers an EEH. We are working with the vendor to ensure that the hardware is not at fault, but if we use the "new" interface (RTAS_CHANGE_MSI_FN) to disable MSI, we also automatically disable MSI-X and the adapter does not appear to signal any stray MSI-X interrupt. Signed-off-by:
Nishanth Aravamudan <nacc@us.ibm.com> Acked-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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- 10 Mar, 2011 28 commits
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Lennert Buytenhek authored
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Lennert Buytenhek <buytenh@secretlab.ca> Acked-by:
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Lennert Buytenhek authored
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- 04 Mar, 2011 2 commits
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Nishanth Aravamudan authored
If firmware allows us to map all of a partition's memory for DMA on a particular bridge, create a 1:1 mapping of that memory. Add hooks for dealing with hotplug events. Dynamic DMA windows can use larger than the default page size, and we use the largest one possible. Signed-off-by:
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Tseng-Hui (Frank) Lin authored
Move SPRN_PID declearations in various locations into one place. Signed-off-by:
Tseng-Hui (Frank) Lin <thlin@linux.vnet.ibm.com> Signed-off-by:
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