1. 12 Nov, 2020 10 commits
    • Nishanth Menon's avatar
      arm64: dts: ti: k3-am65*/j721e*: Fix unit address format error for dss node · cfbf17e6
      Nishanth Menon authored
      Fix the node address to follow the device tree convention.
      
      This fixes the dtc warning:
      <stdout>: Warning (simple_bus_reg): /bus@100000/dss@04a00000: simple-bus
      unit address format error, expected "4a00000"
      
      Fixes: 76921f15 ("arm64: dts: ti: k3-j721e-main: Add DSS node")
      Fixes: fc539b90 ("arm64: dts: ti: am654: Add DSS node")
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarJyri Sarha <jsarha@ti.com>
      Reviewed-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Jyri Sarha <jsarha@ti.com>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Link: https://lore.kernel.org/r/20201104222519.12308-1-nm@ti.com
      cfbf17e6
    • Suman Anna's avatar
      arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs · 0f191152
      Suman Anna authored
      Two carveout reserved memory nodes each have been added for each of the
      R5F remote processor devices within both the MCU and MAIN domains for the
      TI J721E EVM boards. These nodes are assigned to the respective rproc
      device nodes as well. The first region will be used as the DMA pool for
      the rproc device, and the second region will furnish the static carveout
      regions for the firmware memory.
      
      The current carveout addresses and sizes are defined statically for each
      device. The R5F processors do not have an MMU, and as such require the
      exact memory used by the firmwares to be set-aside. The firmware images
      do not require any RSC_CARVEOUT entries in their resource tables either
      to allocate the memory for firmware memory segments.
      
      Note that the R5F1 carveouts are needed only if the R5F cluster is running
      in Split (non-LockStep) mode. The reserved memory nodes can be disabled
      later on if there is no use-case defined to use the corresponding
      remote processor.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-9-s-anna@ti.com
      0f191152
    • Suman Anna's avatar
      arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs · 2879b593
      Suman Anna authored
      Add the required 'mboxes' property to all the R5F processors for the
      TI J721E common processor board. The mailboxes and some shared memory
      are required for running the Remote Processor Messaging (RPMsg) stack
      between the host processor and each of the R5Fs. The nodes are therefore
      added in the common k3-j721e-som-p0.dtsi file so that all of these can
      be co-located.
      
      The chosen sub-mailboxes match the values used in the current firmware
      images. This can be changed, if needed, as per the system integration
      needs after making appropriate changes on the firmware side as well.
      
      Note that any R5F Core1 resources are needed and used only when that
      R5F cluster is configured for Split-mode.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-8-s-anna@ti.com
      2879b593
    • Suman Anna's avatar
      arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes · df445ff9
      Suman Anna authored
      The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
      subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
      the MCU domain, and the remaining two clusters are present in the
      MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
      configured at boot time to be either run in a LockStep mode or in
      an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
      subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
      memories for each core split between two banks - ATCM and BTCM
      (further interleaved into two banks). There are some IP integration
      differences from standard Arm R5 clusters such as the absence of
      an ACP port, presence of an additional TI-specific Region Address
      Translater (RAT) module for translating 32-bit CPU addresses into
      larger system bus addresses etc.
      
      Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
      the two R5F cores are each added as child nodes to the corresponding
      main cluster node. Both the clusters are configured to run in LockStep
      mode by default, with the ATCMs enabled to allow the R5 cores to execute
      code from DDR with boot-strapping code from ATCM. The inter-processor
      communication between the main A72 cores and these processors is
      achieved through shared memory and Mailboxes.
      
      The following firmware names are used by default for these cores, and
      can be overridden in a board dts file if needed:
          MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes)
          MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode)
          MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes)
          MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode)
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-7-s-anna@ti.com
      df445ff9
    • Suman Anna's avatar
      arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node · dd74c945
      Suman Anna authored
      The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
      subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
      the MCU domain, and the remaining two clusters are present in the
      MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
      configured at boot time to be either run in a LockStep mode or in
      an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
      subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
      memories for each core split between two banks - ATCM and BTCM
      (further interleaved into two banks). There are some IP integration
      differences from standard Arm R5 clusters such as the absence of
      an ACP port, presence of an additional TI-specific Region Address
      Translater (RAT) module for translating 32-bit CPU addresses into
      larger system bus addresses etc.
      
      Add the DT node for the MCU domain R5F cluster/subsystem, the two
      R5F cores are added as child nodes to the main cluster/subsystem node.
      The cluster is configured to run in LockStep mode by default, with the
      ATCMs enabled to allow the R5 cores to execute code from DDR with
      boot-strapping code from ATCM. The inter-processor communication
      between the main A72 cores and these processors is achieved through
      shared memory and Mailboxes.
      
      The following firmware names are used by default for these cores, and
      can be overridden in a board dts file if needed:
          MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes)
          MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode)
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-6-s-anna@ti.com
      dd74c945
    • Suman Anna's avatar
      arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores · f82c5e0a
      Suman Anna authored
      Add a reserved memory node to reserve a portion of the DDR memory to be
      used for performing inter-processor communication between all the MCU R5F
      remote processors running RTOS on all the TI AM654 boards. This memory
      shall be exercised only if the MCU R5FSS cluster is configured for Split
      mode.  A single 1 MB of memory at 0xa2000000 is reserved for this purpose,
      and this accounts for all the vrings and vring buffers between pair of
      these R5F remote processors.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-5-s-anna@ti.com
      f82c5e0a
    • Suman Anna's avatar
      arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs · 954ec513
      Suman Anna authored
      The R5F processors do not have an MMU, and as such require the exact memory
      used by the firmwares to be set-aside. Four carveout reserved memory nodes
      have been added with two each (1 MB and 15 MB in size) used for each of the
      MCU R5F remote processor devices on all the TI K3 AM65x boards. These nodes
      are assigned to the respective rproc device nodes as well.
      
      The current carveout addresses and sizes are defined statically for each
      device. The first region will be used as the DMA pool for the rproc
      device, and the second region will furnish the static carveout regions
      for the firmware memory.
      
      Note that the R5F1 carveouts are needed only if the corresponding R5F
      cluster is running in Split (non-LockStep) mode. The corresponding
      reserved memory nodes can be disabled later on if there is no use-case
      defined to use the corresponding remote processor.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-4-s-anna@ti.com
      954ec513
    • Suman Anna's avatar
      arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs · 10332cd6
      Suman Anna authored
      Add the required 'mboxes' property to both the R5F processors on all the
      TI K3 AM65x boards. The mailboxes and some shared memory are required
      for running the Remote Processor Messaging (RPMsg) stack between the
      host processor and each of the R5Fs. The chosen sub-mailboxes match the
      values used in the current firmware images. This can be changed, if
      needed, as per the system integration needs after making appropriate
      changes on the firmware side as well.
      
      Note that the R5F Core1 resources are needed and used only when the
      R5F cluster is configured for Split-mode.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-3-s-anna@ti.com
      10332cd6
    • Suman Anna's avatar
      arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node · 5bb9e0f6
      Suman Anna authored
      The AM65x SoCs have a single dual-core Arm Cortex-R5F processor (R5FSS)
      subsystem/cluster. This R5F cluster (MCU_R5FSS0) is present within the
      MCU domain, and can be configured at boot time to be either run in a
      LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in
      Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM)
      internal memories for each core split between two banks - TCMA and TCMB
      (further interleaved into two banks). There are some IP integration
      differences from standard Arm R5F clusters such as the absence of an ACP
      port, presence of an additional TI-specific Region Address Translater
      (RAT) module for translating 32-bit CPU addresses into larger system
      bus addresses etc.
      
      Add the DT node for this R5F cluster/subsystem, the two R5F cores are
      added as child nodes to the main cluster node. The cluster is configured
      to run in LockStep mode by default, with the ATCMs enabled to allow the
      R5 cores to execute code from DDR with boot-strapping code from ATCM.
      The inter-processor communication between the main A53 cores and these
      processors is achieved through shared memory and Mailboxes.
      
      The following firmware names are used by default for these cores, and
      can be overridden in a board dts file if needed:
          am65x-mcu-r5f0_0-fw (LockStep mode and for Core0 in Split mode)
          am65x-mcu-r5f0_1-fw (Core1 in Split mode)
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Reviewed-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
      Link: https://lore.kernel.org/r/20201029033802.15366-2-s-anna@ti.com
      5bb9e0f6
    • Tomi Valkeinen's avatar
      arm64: dts: ti: k3-am65: mark dss as dma-coherent · 50301e88
      Tomi Valkeinen authored
      DSS is IO coherent on AM65, so we should mark it as such with
      'dma-coherent' property in the DT file.
      
      Fixes: fc539b90 ("arm64: dts: ti: am654: Add DSS node")
      Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Acked-by: default avatarNikhil Devshatwar <nikhil.nd@ti.com>
      Cc: stable@vger.kernel.org # v5.8+
      Link: https://lore.kernel.org/r/20201102134650.55321-1-tomi.valkeinen@ti.com
      50301e88
  2. 26 Oct, 2020 1 commit
  3. 25 Oct, 2020 17 commits
  4. 24 Oct, 2020 12 commits
    • Linus Torvalds's avatar
      Merge tag 'block-5.10-2020-10-24' of git://git.kernel.dk/linux-block · d7691390
      Linus Torvalds authored
      Pull block fixes from Jens Axboe:
      
       - NVMe pull request from Christoph
           - rdma error handling fixes (Chao Leng)
           - fc error handling and reconnect fixes (James Smart)
           - fix the qid displace when tracing ioctl command (Keith Busch)
           - don't use BLK_MQ_REQ_NOWAIT for passthru (Chaitanya Kulkarni)
           - fix MTDT for passthru (Logan Gunthorpe)
           - blacklist Write Same on more devices (Kai-Heng Feng)
           - fix an uninitialized work struct (zhenwei pi)"
      
       - lightnvm out-of-bounds fix (Colin)
      
       - SG allocation leak fix (Doug)
      
       - rnbd fixes (Gioh, Guoqing, Jack)
      
       - zone error translation fixes (Keith)
      
       - kerneldoc markup fix (Mauro)
      
       - zram lockdep fix (Peter)
      
       - Kill unused io_context members (Yufen)
      
       - NUMA memory allocation cleanup (Xianting)
      
       - NBD config wakeup fix (Xiubo)
      
      * tag 'block-5.10-2020-10-24' of git://git.kernel.dk/linux-block: (27 commits)
        block: blk-mq: fix a kernel-doc markup
        nvme-fc: shorten reconnect delay if possible for FC
        nvme-fc: wait for queues to freeze before calling update_hr_hw_queues
        nvme-fc: fix error loop in create_hw_io_queues
        nvme-fc: fix io timeout to abort I/O
        null_blk: use zone status for max active/open
        nvmet: don't use BLK_MQ_REQ_NOWAIT for passthru
        nvmet: cleanup nvmet_passthru_map_sg()
        nvmet: limit passthru MTDS by BIO_MAX_PAGES
        nvmet: fix uninitialized work for zero kato
        nvme-pci: disable Write Zeroes on Sandisk Skyhawk
        nvme: use queuedata for nvme_req_qid
        nvme-rdma: fix crash due to incorrect cqe
        nvme-rdma: fix crash when connect rejected
        block: remove unused members for io_context
        blk-mq: remove the calling of local_memory_node()
        zram: Fix __zram_bvec_{read,write}() locking order
        skd_main: remove unused including <linux/version.h>
        sgl_alloc_order: fix memory leak
        lightnvm: fix out-of-bounds write to array devices->info[]
        ...
      d7691390
    • Linus Torvalds's avatar
      Merge tag 'io_uring-5.10-2020-10-24' of git://git.kernel.dk/linux-block · af004187
      Linus Torvalds authored
      Pull io_uring fixes from Jens Axboe:
      
       - fsize was missed in previous unification of work flags
      
       - Few fixes cleaning up the flags unification creds cases (Pavel)
      
       - Fix NUMA affinities for completely unplugged/replugged node for io-wq
      
       - Two fallout fixes from the set_fs changes. One local to io_uring, one
         for the splice entry point that io_uring uses.
      
       - Linked timeout fixes (Pavel)
      
       - Removal of ->flush() ->files work-around that we don't need anymore
         with referenced files (Pavel)
      
       - Various cleanups (Pavel)
      
      * tag 'io_uring-5.10-2020-10-24' of git://git.kernel.dk/linux-block:
        splice: change exported internal do_splice() helper to take kernel offset
        io_uring: make loop_rw_iter() use original user supplied pointers
        io_uring: remove req cancel in ->flush()
        io-wq: re-set NUMA node affinities if CPUs come online
        io_uring: don't reuse linked_timeout
        io_uring: unify fsize with def->work_flags
        io_uring: fix racy REQ_F_LINK_TIMEOUT clearing
        io_uring: do poll's hash_node init in common code
        io_uring: inline io_poll_task_handler()
        io_uring: remove extra ->file check in poll prep
        io_uring: make cached_cq_overflow non atomic_t
        io_uring: inline io_fail_links()
        io_uring: kill ref get/drop in personality init
        io_uring: flags-based creds init in queue
      af004187
    • Linus Torvalds's avatar
      Merge tag 'libata-5.10-2020-10-24' of git://git.kernel.dk/linux-block · cb6b2897
      Linus Torvalds authored
      Pull libata fixes from Jens Axboe:
       "Two minor libata fixes:
      
         - Fix a DMA boundary mask regression for sata_rcar (Geert)
      
         - kerneldoc markup fix (Mauro)"
      
      * tag 'libata-5.10-2020-10-24' of git://git.kernel.dk/linux-block:
        ata: fix some kernel-doc markups
        ata: sata_rcar: Fix DMA boundary mask
      cb6b2897
    • Linus Torvalds's avatar
      Merge branch 'work.misc' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs · 0eac1102
      Linus Torvalds authored
      Pull misc vfs updates from Al Viro:
       "Assorted stuff all over the place (the largest group here is
        Christoph's stat cleanups)"
      
      * 'work.misc' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
        fs: remove KSTAT_QUERY_FLAGS
        fs: remove vfs_stat_set_lookup_flags
        fs: move vfs_fstatat out of line
        fs: implement vfs_stat and vfs_lstat in terms of vfs_fstatat
        fs: remove vfs_statx_fd
        fs: omfs: use kmemdup() rather than kmalloc+memcpy
        [PATCH] reduce boilerplate in fsid handling
        fs: Remove duplicated flag O_NDELAY occurring twice in VALID_OPEN_FLAGS
        selftests: mount: add nosymfollow tests
        Add a "nosymfollow" mount option.
      0eac1102
    • Linus Torvalds's avatar
      Merge tag 'dma-mapping-5.10-1' of git://git.infradead.org/users/hch/dma-mapping · 1b307ac8
      Linus Torvalds authored
      Pull dma-mapping fixes from Christoph Hellwig:
      
       - document the new dma_{alloc,free}_pages() API
      
       - two fixups for the dma-mapping.h split
      
      * tag 'dma-mapping-5.10-1' of git://git.infradead.org/users/hch/dma-mapping:
        dma-mapping: document dma_{alloc,free}_pages
        dma-mapping: move more functions to dma-map-ops.h
        ARM/sa1111: add a missing include of dma-map-ops.h
      1b307ac8
    • Linus Torvalds's avatar
      Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm · 9bf8d8bc
      Linus Torvalds authored
      Pull KVM fixes from Paolo Bonzini:
       "Two fixes for this merge window, and an unrelated bugfix for a host
        hang"
      
      * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
        KVM: ioapic: break infinite recursion on lazy EOI
        KVM: vmx: rename pi_init to avoid conflict with paride
        KVM: x86/mmu: Avoid modulo operator on 64-bit value to fix i386 build
      9bf8d8bc
    • Linus Torvalds's avatar
      Merge tag 'x86_seves_fixes_for_v5.10_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip · c51ae124
      Linus Torvalds authored
      Pull x86 SEV-ES fixes from Borislav Petkov:
       "Three fixes to SEV-ES to correct setting up the new early pagetable on
        5-level paging machines, to always map boot_params and the kernel
        cmdline, and disable stack protector for ../compressed/head{32,64}.c.
        (Arvind Sankar)"
      
      * tag 'x86_seves_fixes_for_v5.10_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
        x86/boot/64: Explicitly map boot_params and command line
        x86/head/64: Disable stack protection for head$(BITS).o
        x86/boot/64: Initialize 5-level paging variables earlier
      c51ae124
    • Willy Tarreau's avatar
      random32: add a selftest for the prandom32 code · c6e169bc
      Willy Tarreau authored
      Given that this code is new, let's add a selftest for it as well.
      It doesn't rely on fixed sets, instead it picks 1024 numbers and
      verifies that they're not more correlated than desired.
      
      Link: https://lore.kernel.org/netdev/20200808152628.GA27941@SDF.ORG/
      Cc: George Spelvin <lkml@sdf.org>
      Cc: Amit Klein <aksecurity@gmail.com>
      Cc: Eric Dumazet <edumazet@google.com>
      Cc: "Jason A. Donenfeld" <Jason@zx2c4.com>
      Cc: Andy Lutomirski <luto@kernel.org>
      Cc: Kees Cook <keescook@chromium.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: tytso@mit.edu
      Cc: Florian Westphal <fw@strlen.de>
      Cc: Marc Plumb <lkml.mplumb@gmail.com>
      Signed-off-by: default avatarWilly Tarreau <w@1wt.eu>
      c6e169bc
    • Willy Tarreau's avatar
      random32: add noise from network and scheduling activity · 3744741a
      Willy Tarreau authored
      With the removal of the interrupt perturbations in previous random32
      change (random32: make prandom_u32() output unpredictable), the PRNG
      has become 100% deterministic again. While SipHash is expected to be
      way more robust against brute force than the previous Tausworthe LFSR,
      there's still the risk that whoever has even one temporary access to
      the PRNG's internal state is able to predict all subsequent draws till
      the next reseed (roughly every minute). This may happen through a side
      channel attack or any data leak.
      
      This patch restores the spirit of commit f227e3ec ("random32: update
      the net random state on interrupt and activity") in that it will perturb
      the internal PRNG's statee using externally collected noise, except that
      it will not pick that noise from the random pool's bits nor upon
      interrupt, but will rather combine a few elements along the Tx path
      that are collectively hard to predict, such as dev, skb and txq
      pointers, packet length and jiffies values. These ones are combined
      using a single round of SipHash into a single long variable that is
      mixed with the net_rand_state upon each invocation.
      
      The operation was inlined because it produces very small and efficient
      code, typically 3 xor, 2 add and 2 rol. The performance was measured
      to be the same (even very slightly better) than before the switch to
      SipHash; on a 6-core 12-thread Core i7-8700k equipped with a 40G NIC
      (i40e), the connection rate dropped from 556k/s to 555k/s while the
      SYN cookie rate grew from 5.38 Mpps to 5.45 Mpps.
      
      Link: https://lore.kernel.org/netdev/20200808152628.GA27941@SDF.ORG/
      Cc: George Spelvin <lkml@sdf.org>
      Cc: Amit Klein <aksecurity@gmail.com>
      Cc: Eric Dumazet <edumazet@google.com>
      Cc: "Jason A. Donenfeld" <Jason@zx2c4.com>
      Cc: Andy Lutomirski <luto@kernel.org>
      Cc: Kees Cook <keescook@chromium.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: tytso@mit.edu
      Cc: Florian Westphal <fw@strlen.de>
      Cc: Marc Plumb <lkml.mplumb@gmail.com>
      Tested-by: default avatarSedat Dilek <sedat.dilek@gmail.com>
      Signed-off-by: default avatarWilly Tarreau <w@1wt.eu>
      3744741a
    • George Spelvin's avatar
      random32: make prandom_u32() output unpredictable · c51f8f88
      George Spelvin authored
      Non-cryptographic PRNGs may have great statistical properties, but
      are usually trivially predictable to someone who knows the algorithm,
      given a small sample of their output.  An LFSR like prandom_u32() is
      particularly simple, even if the sample is widely scattered bits.
      
      It turns out the network stack uses prandom_u32() for some things like
      random port numbers which it would prefer are *not* trivially predictable.
      Predictability led to a practical DNS spoofing attack.  Oops.
      
      This patch replaces the LFSR with a homebrew cryptographic PRNG based
      on the SipHash round function, which is in turn seeded with 128 bits
      of strong random key.  (The authors of SipHash have *not* been consulted
      about this abuse of their algorithm.)  Speed is prioritized over security;
      attacks are rare, while performance is always wanted.
      
      Replacing all callers of prandom_u32() is the quick fix.
      Whether to reinstate a weaker PRNG for uses which can tolerate it
      is an open question.
      
      Commit f227e3ec ("random32: update the net random state on interrupt
      and activity") was an earlier attempt at a solution.  This patch replaces
      it.
      Reported-by: default avatarAmit Klein <aksecurity@gmail.com>
      Cc: Willy Tarreau <w@1wt.eu>
      Cc: Eric Dumazet <edumazet@google.com>
      Cc: "Jason A. Donenfeld" <Jason@zx2c4.com>
      Cc: Andy Lutomirski <luto@kernel.org>
      Cc: Kees Cook <keescook@chromium.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: tytso@mit.edu
      Cc: Florian Westphal <fw@strlen.de>
      Cc: Marc Plumb <lkml.mplumb@gmail.com>
      Fixes: f227e3ec ("random32: update the net random state on interrupt and activity")
      Signed-off-by: default avatarGeorge Spelvin <lkml@sdf.org>
      Link: https://lore.kernel.org/netdev/20200808152628.GA27941@SDF.ORG/
      [ willy: partial reversal of f227e3ec; moved SIPROUND definitions
        to prandom.h for later use; merged George's prandom_seed() proposal;
        inlined siprand_u32(); replaced the net_rand_state[] array with 4
        members to fix a build issue; cosmetic cleanups to make checkpatch
        happy; fixed RANDOM32_SELFTEST build ]
      Signed-off-by: default avatarWilly Tarreau <w@1wt.eu>
      c51f8f88
    • Linus Torvalds's avatar
      Merge tag 'powerpc-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux · b6f96e75
      Linus Torvalds authored
      Pull powerpc fixes from Michael Ellerman:
      
       - A fix for undetected data corruption on Power9 Nimbus <= DD2.1 in the
         emulation of VSX loads. The affected CPUs were not widely available.
      
       - Two fixes for machine check handling in guests under PowerVM.
      
       - A fix for our recent changes to SMP setup, when
         CONFIG_CPUMASK_OFFSTACK=y.
      
       - Three fixes for races in the handling of some of our powernv sysfs
         attributes.
      
       - One change to remove TM from the set of Power10 CPU features.
      
       - A couple of other minor fixes.
      
      Thanks to: Aneesh Kumar K.V, Christophe Leroy, Ganesh Goudar, Jordan
      Niethe, Mahesh Salgaonkar, Michael Neuling, Oliver O'Halloran, Qian Cai,
      Srikar Dronamraju, Vasant Hegde.
      
      * tag 'powerpc-5.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
        powerpc/pseries: Avoid using addr_to_pfn in real mode
        powerpc/uaccess: Don't use "m<>" constraint with GCC 4.9
        powerpc/eeh: Fix eeh_dev_check_failure() for PE#0
        powerpc/64s: Remove TM from Power10 features
        selftests/powerpc: Make alignment handler test P9N DD2.1 vector CI load workaround
        powerpc: Fix undetected data corruption with P9N DD2.1 VSX CI load emulation
        powerpc/powernv/dump: Handle multiple writes to ack attribute
        powerpc/powernv/dump: Fix race while processing OPAL dump
        powerpc/smp: Use GFP_ATOMIC while allocating tmp mask
        powerpc/smp: Remove unnecessary variable
        powerpc/mce: Avoid nmi_enter/exit in real mode on pseries hash
        powerpc/opal_elog: Handle multiple writes to ack attribute
      b6f96e75
    • Linus Torvalds's avatar
      Merge tag 'riscv-for-linus-5.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux · 0593c1b4
      Linus Torvalds authored
      Pull more RISC-V updates from Palmer Dabbelt:
       "Just a single patch set: the remainder of Christoph's work to remove
        set_fs, including the RISC-V portion"
      
      * tag 'riscv-for-linus-5.10-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
        riscv: remove address space overrides using set_fs()
        riscv: implement __get_kernel_nofault and __put_user_nofault
        riscv: refactor __get_user and __put_user
        riscv: use memcpy based uaccess for nommu again
        asm-generic: make the set_fs implementation optional
        asm-generic: add nommu implementations of __{get,put}_kernel_nofault
        asm-generic: improve the nommu {get,put}_user handling
        uaccess: provide a generic TASK_SIZE_MAX definition
      0593c1b4