- 06 Apr, 2023 8 commits
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Kathiravan T authored
Add the nodes for QUP peripheral, PRNG and WDOG. While at it, enable the I2C device for MI01.2 board. Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230320104530.30411-3-quic_kathirav@quicinc.com
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Krzysztof Kozlowski authored
Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8550. The nodes are very similar to SM8450, except missing NPL clock which is not exposed on SM8550 and should not be touched. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Manivannan Sadhasivam authored
Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map" properties for the PCIe nodes. First one passes the SMR mask to the iommu driver and the latter specifies the SID for each PCIe device. But with "iommus" property, the PCIe controller will be added to the iommu group along with the devices. This makes no sense because the controller will not initiate any DMA transaction on its own. And moreover, it is not strictly required to pass the SMR mask to the iommu driver. If the "iommus" property is not present, then the default mask of "0" would be used which should work for all PCIe devices. On the other side, if the SMR mask specified doesn't match the one expected by the hypervisor, then all the PCIe transactions will end up triggering "Unidentified Stream Fault" by the SMMU. So to get rid of these hassles and also prohibit PCIe controllers from adding to the iommu group, let's remove the "iommus" property from PCIe nodes. Reported-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.orgSigned-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
The parent controller for the interrupt is GIC, so no need for interrupts-extended. Signed-off-by:
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Krzysztof Kozlowski authored
The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by:
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Krzysztof Kozlowski authored
Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by:
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Krzysztof Kozlowski authored
Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by:
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- 05 Apr, 2023 32 commits
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Konrad Dybcio authored
Use the non-deprecated, SoC-specific DSI compatible. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
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Steev Klimaszewski authored
The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2, add this. Signed-off-by:
Steev Klimaszewski <steev@kali.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Tested-by:
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Bjorn Andersson authored
Add the definition for uart2 for sc8280xp devices. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Brian Masney <bmasney@redhat.com> Reviewed-by:
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Manivannan Sadhasivam authored
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by:
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Manivannan Sadhasivam authored
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by:
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Manivannan Sadhasivam authored
The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by:
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Bartosz Golaszewski authored
Set line names for GPIO lines exposed by PMICs on sa8775p-ride. Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by:
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Bartosz Golaszewski authored
Add GPIO controller nodes to PMICs that have the GPIO hooked up on sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add the thermal zones and associated alarm nodes for the PMICs that have them hooked up on sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add the RESIN input for sa8775p platforms' PMIC. Signed-off-by:
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Bartosz Golaszewski authored
Add the power key node under the PON node for PMIC #0 on sa8775p. Signed-off-by:
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Bartosz Golaszewski authored
Add the PON node to PMIC #0 for sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced to the SoC via SPMI. Enable the PMICs for sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add the SPMI PMIC Arbiter node for SA8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add the Power Domain Controller node for SA8775p. Signed-off-by:
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Bartosz Golaszewski authored
Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency. Signed-off-by:
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Bartosz Golaszewski authored
The file has inconsistent padding of the address part of soc node children's reg properties. Fix it. Signed-off-by:
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Krzysztof Kozlowski authored
The bindings expect second Soundwire interrupt to be "wakeup" (Linux driver takes by index): sc8280xp-crd.dtb: soundwire-controller@3330000: interrupt-names:1: 'wakeup' was expected Fixes: c18773d1 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS") Signed-off-by:
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Konrad Dybcio authored
Enable both GPI DMAs. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Konrad Dybcio authored
Enable the A630 GPU and its GMU. Signed-off-by:
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Konrad Dybcio authored
Enable ADSP, CDSP and Venus. Signed-off-by:
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Konrad Dybcio authored
Add the properties to ensure the ever so delicate touchscreen setup matches downstream. Signed-off-by:
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Konrad Dybcio authored
Add required pins and RMI4 node to the common DT and remove it from Akatsuki, as it uses a different touch. Since the panels are super high tech proprietary incell, they need to be handled with very precise timings. As such the panel driver sets up the power rails and GPIOs and the touchscreen driver *has to* probe afterwards. Signed-off-by:
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Konrad Dybcio authored
Add required nodes to support display on XZ2/XZ2c. XZ3 has a different power rail setup and needs to be handled separately. Signed-off-by:
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Adam Skladowski authored
Follow other dtses and pad regs to 8 digits. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Reviewed-by:
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Adam Skladowski authored
Property phy_mode according to binding checker does not exist, drop it. Signed-off-by:
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Adam Skladowski authored
Provide clocks from dsi_phy to gcc, this will make sure we don't fallback to global name lookup. Signed-off-by:
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Adam Skladowski authored
Assign RPM_SMD_XO_CLK_SRC from rpmcc in place of fixed-clock where possible. Signed-off-by:
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Neil Armstrong authored
Fixes the following DT bindings check error: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Domain idle states do not use 'idle-state-name': sc8280xp-crd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+' Reported-by:
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Krzysztof Kozlowski authored
Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8350-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by:
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Krzysztof Kozlowski authored
Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8150-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by:
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