- 25 May, 2011 40 commits
-
-
Andrei Warkentin authored
CMD23-prefixed instead of open-ended multiblock transfers have a performance advantage on some MMC cards. Signed-off-by:
Andrei Warkentin <andreiw@motorola.com> Signed-off-by:
Chris Ball <cjb@laptop.org>
-
Andrei Warkentin authored
Conditional add/remove quirks for MMC and SD. Signed-off-by:
-
Tony Olech authored
Add a driver for Elan Digital System's VUB300 chip which is a USB connected SDIO/SDmem/MMC host controller. A VUB300 chip enables a USB 2.0 or USB 1.1 connected host computer to use SDIO/SD/MMC cards without the need for a directly connected, for example via PCI, SDIO host controller. Signed-off-by:
Anthony F Olech <tony.olech@elandigitalsystems.com> [cjb: various punctuation and style fixes] Tested-by:
-
Philip Rakity authored
32 Bit DMA/ADMA Access 32 Bit Size Support ADMA End Descriptor in current chain (no need for dummy entry) Signed-off-by:
Philip Rakity <prakity@marvell.com> Tested-by:
-
Jaehoon Chung authored
mmc_rescan_try_freq() tries to init two times with the last frequency. For example, if host->f_min is 400KHz, we see the message below: mmc1: mmc_rescan_try_freq: trying to init card at 400000 Hz mmc1: mmc_rescan_try_freq: trying to init card at 400000 Hz Andy Ross says that he didn't try this code on a board with an f_min that exactly matches one of the table entries, which explains why the bug wasn't detected. Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Cc: Andy Ross <andy.ross@windriver.com> Signed-off-by:
-
Philip Rakity authored
eMMC voltage change not required for 1.8V. 3.3V and 1.8V vcc are capable of doing DDR. vccq of 1.8v is not required. Signed-off-by:
Arindam Nath <arindam.nath@amd.com> Signed-off-by:
-
Philip Rakity authored
eMMC chips do not use CMD11 when changing voltage. Add extra argument to call to indicate if CMD11 needs to be sent. Signed-off-by:
-
Philip Rakity authored
Marvell controller requires 1.8V bit in UHS control register 2 be set when doing UHS. eMMC does not require 1.8V for DDR. add platform code to handle this. Signed-off-by:
-
Philip Rakity authored
Allow platform specific code to set UHS registers if implementation requires speciial platform specific handling Signed-off-by:
-
Eliad Peller authored
Since the MMC_PM_KEEP_POWER flag should be set on each suspend, it should also cleared on each resume. Upon resuming, we have to know if power was kept (for re-initialization, etc.), so clear it just after resuming. Signed-off-by:
Eliad Peller <eliad@wizery.com> Signed-off-by:
-
Jaehoon Chung authored
regulator_enable() was incorrectly placed in the suspend function instead of the resume function. Signed-off-by:
Will Newton <will.newton@imgtec.com> Signed-off-by:
-
Guennadi Liakhovetski authored
Supply a link to TMIO private data for platforms to implement their own card detection. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
-
Guennadi Liakhovetski authored
The TMIO MMC controller cannot be powered off to save power, when no card is plugged in, because then it will not be able to detect a new card-insertion event. On some implementations, however, it is possible to switch to using another source to detect card insertion. This patch adds support for such implementations. Signed-off-by:
-
Magnus Damm authored
Convert the SDHI code to support more than a single interrupt source. Needed to support hardware that uses GIC instead of INTC as interrupt controller. Will also allow us to remove the irq forwarding workaround from the INTC code in the future. Signed-off-by:
Simon Horman <horms@verge.net.au> Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
-
Magnus Damm authored
Instead of printing out useless information such as the virtual base address and one of 4 interrupts, convert the SDHI probe() to print out physical base address together with clock rate. We do have a struct device so make use of dev_info(). Signed-off-by:
-
Magnus Damm authored
Modify the SDHI driver to get rid of unwanted irq flags. IRQF_DISABLED unused, see include/linux/interrupt.h IRQF_TRIGGER_FALLING only relevant on external IRQ pins, but since SDHI is internal in the SoC this can go away. Needed to support SDHI on sh73a0 that comes with a GIC that errors out with the IRQF_TRIGGER_FALLING setting. Signed-off-by:
-
Magnus Damm authored
Move request_irq()/free_irq() from the shared code in tmio_mmc.c into the SDHI/tmio specific portion in sh_mobile_sdhi.c and tmio_mmc_pio.c. This is ground work to allow us to adjust the SDHI code with IRQ flags and number of interupt sources. Signed-off-by:
-
Guennadi Liakhovetski authored
The MMC subsystem does not guarantee, that host driver .request() and .set_ios() callbacks are serialised. Such concurrent calls, however, do not have to be meaningfully supported, drivers just have to make sure to avoid any severe problems. Signed-off-by:
-
Guennadi Liakhovetski authored
Adding support for runtime power-management to the MMCIF driver allows it to save power as long as no card is present. To also allow to turn off the power domain at that time, we release DMA channels during that time, since on some sh-mobile systems the DMA controller(s) and the MMCIF block belong to the same power domain. System-wide power management has been tested with experimental PM patches on AP4-based systems. Signed-off-by:
-
Guennadi Liakhovetski authored
Add runtime and system-wide power management to the TMIO MMC driver in PIO and DMA modes, allowing it to properly save and restore its state during system suspend. Runtime PM is very crude ATM, because the controller has to be powered on all the time to detect card hotplug events. Signed-off-by:
-
Guennadi Liakhovetski authored
The MMC subsystem does not guarantee that host driver .request() and .set_ios() callbacks are serialised. Such concurrent calls, however, do not have to be meaningfully supported, drivers just have to make sure to avoid any severe problems. Signed-off-by:
-
Stefan Nilsson XK authored
If there is only 1 function interrupt registered it is possible to improve performance by directly calling the irq handler and avoiding the overhead of reading the CCCR registers. Signed-off-by:
Per Forlin <per.forlin@linaro.org> Acked-by:
Ulf Hansson <ulf.hansson@stericsson.com> Reviewed-by:
Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by:
-
Andy Shevchenko authored
Signed-off-by:
Andy Shevchenko <ext-andriy.shevchenko@nokia.com> Signed-off-by:
-
Vladimir Motyka authored
When allocation of idata failed there was a null dereference. Also avoid calling kfree where it isn't needed. Signed-off-by:
Vladimir Motyka <vladimir.motyka@gmail.com> Signed-off-by:
-
Arindam Nath authored
Host Controller v3.00 can support retuning modes 1,2 or 3 depending on the bits 46-47 of the Capabilities register. Also, the timer count for retuning is indicated by bits 40-43 of the same register. We initialize timer_list for retuning the first time we execute tuning procedure. This condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since retuning mode 1 sets a limit of 4MB on the maximum data length, we set max_blk_count appropriately. Once the tuning timer expires, we set SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning procedure before sending the next command. We need to restore mmc_request structure after executing retuning procedure since host->mrq is used inside the procedure to send CMD19. We also disable and re-enable this flag during suspend and resume respectively, as per the spec v3.00. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by:
-
Arindam Nath authored
Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
According to the Host Controller spec v3.00, setting Preset Value Enable in the Host Control2 register lets SDCLK Frequency Select, Clock Generator Select and Driver Strength Select to be set automatically by the Host Controller based on the UHS-I mode set. This patch enables this feature. Since Preset Value Enable makes sense only for UHS-I cards, we enable this feature after successfull UHS-I initialization. We also reset Preset Value Enable next time before initialization. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
Since only UHS-I cards respond with S18A set in response to ACMD41, we set the card as ultra-high-speed after successfull initialization. We need to decide whether a card is SDXC based on the C_SIZE field of CSDv2.0 register. According to Physical Layer spec v3.01, the minimum value of C_SIZE for SDXC card is 00FFFFh. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
We decide on the current limit to be set for the card based on the Capability of Host Controller to provide current at 1.8V signalling, and the maximum current limit of the card as indicated by CMD6 mode 0. We then set the current limit for the card using CMD6 mode 1. As per the Physical Layer Spec v3.01, the current limit switch is only applicable for SDR50, SDR104, and DDR50 bus speed modes. For other UHS-I modes, we set the default current limit of 200mA. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
This patch adds support for setting UHS-I bus speed mode during UHS-I initialization procedure. Since both the host and card can support more than one bus speed, we select the highest speed based on both of their capabilities. First we set the bus speed mode for the card using CMD6 mode 1, and then we program the host controller to support the required speed mode. We also set High Speed Enable in case one of the UHS-I modes is selected. We take care to reset SD clock before setting UHS mode in the Host Control2 register, and then re-enable it as per the Host Controller spec v3.00. We then set the clock frequency for the UHS-I mode selected. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
As per Host Controller spec v3.00, we reset SDCLK before setting High Speed Enable, and then set it back to avoid generating clock gliches. Before enabling SDCLK again, we make sure the clock is stable, so we use sdhci_set_clock(). Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
This patch adds support for setting driver strength during UHS-I initialization procedure. Since UHS-I cards set S18A (bit 24) in response to ACMD41, we use this as a base for UHS-I initialization. We modify the parameter list of mmc_sd_get_cid() so that we can save the ROCR from ACMD41 to check whether bit 24 is set. We decide whether the Host Controller supports A, C, or D driver type depending on the Capabilities register. Driver type B is suported by default. We then set the appropriate driver type for the card using CMD6 mode 1. As per Host Controller spec v3.00, we set driver type for the host only if Preset Value Enable in the Host Control2 register is not set. SDHCI_HOST_CONTROL has been renamed to SDHCI_HOST_CONTROL1 to conform to the spec. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
SD cards which conform to Physical Layer Spec v3.01 can support additional Bus Speed Modes, Driver Strength, and Current Limit other than the default values. We use CMD6 mode 0 to read these additional card functions. The values read here will be used during UHS-I initialization steps. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
Arindam Nath authored
Host Controller v3.00 adds another Capabilities register. Apart from other things, this new register indicates whether the Host Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec doesn't mention about explicit support for SDR12 and SDR25 UHS-I modes, so the Host Controller v3.00 should support them by default. Also if the controller supports SDR104 mode, it will also support SDR50 mode as well. So depending on the host support, we set the corresponding MMC_CAP_* flags. One more new register. Host Control2 is added in v3.00, which is used during Signal Voltage Switch procedure described below. Since as per v3.00 spec, UHS-I supported hosts should set S18R to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also need to set XPC (bit 28) of OCR in case the host can supply >150mA. This support is indicated by the Maximum Current Capabilities register of the Host Controller. If the response of ACMD41 has both CCS and S18A set, we start the signal voltage switch procedure, which if successfull, will switch the card from 3.3V signalling to 1.8V signalling. Signal voltage switch procedure adds support for a new command CMD11 in the Physical Layer Spec v3.01. As part of this procedure, we need to set 1.8V Signalling Enable (bit 3) of Host Control2 register, which if remains set after 5ms, means the switch to 1.8V signalling is successfull. Otherwise, we clear bit 24 of OCR and retry the initialization sequence. When we remove the card, and insert the same or another card, we need to make sure that we start with 3.3V signalling voltage. So we call mmc_set_signal_voltage() with MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling voltage before we actually start initializing the card. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by:
-
John Calixto authored
Allows appropriately-privileged applications to send CMD (normal) and ACMD (application-specific; preceded with CMD55) commands to cards/devices on the mmc bus. This is primarily useful for enabling the security functionality built in to every SD card. It can also be used as a generic passthrough (e.g. to enable virtual machines to control mmc bus devices directly). However, this use case has not been tested rigorously. Generic passthrough testing was only conducted for a few non-security opcodes to prove the feasibility of the passthrough. Since any opcode can be sent using this passthrough, it is very possible to render the card/device unusable. Applications that use this ioctl must have CAP_SYS_RAWIO. Security commands tested on TI PCIxx12 (SDHCI), Sigma Designs SMP8652 SoC, TI OMAP3621/OMAP3630 SoC, Samsung S5PC110 SoC, Qualcomm MSM7200A SoC. Signed-off-by:
John Calixto <john.calixto@modsystems.com> Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
-
Rabin Vincent authored
To avoid lockdep warnings: BUG: key dc90a520 not in .data! ------------[ cut here ]------------ WARNING: at /home/rabin/kernel/arm/kernel/lockdep.c:2701 sysfs_add_file_mode+0x4c/0xb0() Modules linked in: [<c004b5d8>] (unwind_backtrace+0x0/0xe4) from [<c0074f20>] (warn_slowpath_common+0x4c/0x64) [<c0074f20>] (warn_slowpath_common+0x4c/0x64) from [<c0074f50>] (warn_slowpath_null+0x18/0x1c) [<c0074f50>] (warn_slowpath_null+0x18/0x1c) from [<c0157fec>] (sysfs_add_file_mode+0x4c/0xb0) [<c0157fec>] (sysfs_add_file_mode+0x4c/0xb0) from [<c02d61e4>] (mmc_add_disk+0x40/0x64) [<c02d61e4>] (mmc_add_disk+0x40/0x64) from [<c02d64cc>] (mmc_blk_probe+0x188/0x1fc) [<c02d64cc>] (mmc_blk_probe+0x188/0x1fc) from [<c02ce820>] (mmc_bus_probe+0x14/0x18) ... Signed-off-by:
Rabin Vincent <rabin@rab.in> Signed-off-by:
-
Takashi Iwai authored
On HP laptops with JMicron 388 chip, the write-locked SD card isn't detected correctly as read-only in many cases. This is because the PRESENT_STATE register becomes unsable just after plugging, and it returns the WRITE_PROTECT bit wrongly at the first read. This patch fixes the read-only detection by adding a new sdhci quirk indicating to check the register more intensively with a relatively long delay. The patch is tested with 2.6.39-rc4 kernel. Cc: Aries Lee <arieslee@jmicron.com> Signed-off-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
-
Andrei Warkentin authored
With the hardware partitions support (which represent additional logical devices present on MMC), devidx does not correspond with index used to form /dev/mmcblkX names. So use an additional allocated index for device names. Signed-off-by:
-
Philip Rakity authored
Marvell pxa controllers have private registers that may need to be modified before and after a reset is done. For example, the SD reset operation, RESET_ALL, will reset the private registers to their default state. This will cause the clock adjustment registers that may have been programmed to have incorrect values. RESET_DATA sometimes needs to be delayed before the reset is done (depending on SoC) to enable any transactions being handled by the SDIO card to be completed. Needed in pre SD 3.0 silicon to handle clock gating. Implement hooks to allow this to happen. Signed-off-by:
-
