- 11 Jun, 2014 17 commits
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Ben Skeggs authored
This was a half-finished hack before, just enough to handle the shared aux/i2c pad thing on G94 and up. We got lucky with locking etc up until now, as this was (generally) all protected by the DRM mode_config lock. It's about to become a lot more likely to hit the races. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Re-uses the implementation's accessor functions rather than requiring and init/fini implementation for each chipset. Signed-off-by: -
Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
We really want this for, at least, MST devices. Signed-off-by: -
Ben Skeggs authored
Not enabled at the backends yet, but will read status and send back max reached at level 0. Signed-off-by: -
Ben Skeggs authored
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- 10 Jun, 2014 23 commits
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Ilia Mirkin authored
This fixes hangs on GK208 which happen instantaneously on trying to use a geometry shader. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
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Mario Kleiner authored
Cards with nv04 display engine can't reliably use vblank counts and timestamps computed via drm_handle_vblank(), as the function gets invoked after sending the pageflip events. Fix this by defaulting to the old crtcid = -1 fallback path on <= NV-50 cards, and only using the precise path on NV-50 and later. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
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Mario Kleiner authored
Whenever a single nouveau_mc_intr() main gpu irq-handler invocation was responsible for calling both, the vblank-irq handler (display engine irq) and kms-pageflip completion handler (from fifo irq), the order of invocation was wrong. nouveau_finish_flip() was called before drm_handle_vblank() for the vblank of pageflip completion, so the emitted pageflip event contained stale vblank count and timestamp from previous vblank. This caused failure in userspace to timestamp properly. Reorder order of invocation of engine irq handlers: Put NVDEV_ENGINE_DISP always on top, and thereby before NVDEV_ENGINE_FIFO, so that drm_handle_vblank() gets called to update vblank timestamps and count before potential pageflip events make use of that information. This works on nv-50 and later, where kms-pageflip completion triggers an irq either after a separate vblank irq, or both pageflip and vblank trigger one common irq invocation, but never before vblank irqs. v2 (Ben): - removed mods for nv04-nv40, it doesn't help there anyway - this is considered a hack, and a better solution should be found Signed-off-by:
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Mario Kleiner authored
nv04_disp_scanoutpos() must abort to trigger simple timestamping fallback if vtotal/htotal regs return zero. This happens if the output isn't a digital output, but a vga analog output, as the regs don't get initialized in that case. Fixes timestamping failure on nv-40 and earlier with vga output. Signed-off-by:
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
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Ben Skeggs authored
Leave debug for the more interesting bits of info. Signed-off-by: -
Ilia Mirkin authored
Use with caution. Signed-off-by:
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Ilia Mirkin authored
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Martin Peres authored
Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Martin Peres <martin.peres@free.fr> Signed-off-by:
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Martin Peres authored
Some adt7473 can't manage the 20µs delay we use for the bitbanging, bumping it to 40µs seem to do the trick. Signed-off-by:
Marcel Dopita <mdop@seznam.cz>
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Martin Peres authored
I spent some time this weekend trying to find in the vbios the number of pulses per revolutions in the vbios but couldn't find it. It would seem all my cards have 2 pulses per revolution so let's stick to that until further notice. Thermal table's id 0x48 may indicate this information but it would seem that changing the value results in the blob power or clock gating the RPM counter... We should ask NVIDIA about that, should be trivial-enough for them to answer. Signed-off-by:
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John Rowley authored
Only tested on nvf1, was advised to enable on all. Signed-off-by:
John Rowley <john.rowley08@gmail.com> Signed-off-by:
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John Rowley authored
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Alexandre Courbot authored
Set the correct subdev/engine classes when GK20A (0xea) is probed. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
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Alexandre Courbot authored
Add a GR device for GK20A based on NVE4, with the correct classes definitions (GK20A's 3D class is 0xa297). Most of the NVE4 code can be used on GK20A, so make relevant bits of NVE4 available to other chips as well. Signed-off-by:
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Alexandre Courbot authored
Pad the microcode to a multiple of 0x40 words, otherwise firmware will fail to run from non-prepadded firmware files. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Alexandre Courbot authored
nvc0_graph_ctor() would only let the graphics engine be enabled if its oclass has a proper microcode linked to it. This prevents GR from being enabled at all on chips that rely exclusively on external firmware, even though such a use-case is valid. Relax the conditions enabling the GR engine to also include the case where an external firmware has also been loaded. Also switch to external firmware if the graph class has no microcode linked to it. Signed-off-by:
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Alexandre Courbot authored
GK20A's FIFO is compatible with NVE0, but only features 128 channels and 1 runlist. Signed-off-by:
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Alexandre Courbot authored
Add a simple FB device for GK20A, as well as a RAM implementation suitable for chips that use system memory as video RAM. Signed-off-by:
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Alexandre Courbot authored
Add support for initializing the priv ring of GK20A. This is done by the BIOS on desktop GPUs, but needs to be done by hand on Tegra. Signed-off-by:
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