- 27 Mar, 2023 7 commits
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Jithu Joseph authored
Array BIST is a new type of core test introduced under the Intel Infield Scan (IFS) suite of tests. Emerald Rapids (EMR) is the first CPU to support Array BIST. Array BIST performs tests on some portions of the core logic such as caches and register files. These are different portions of the silicon compared to the parts tested by the first test type i.e Scan at Field (SAF). Make changes in the device driver init flow to register this new test type with the device driver framework. Each test will have its own sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to accommodate for the differences in test type and how they are initiated. Upcoming patches will add actual support. Signed-off-by:
Jithu Joseph <jithu.joseph@intel.com> Reviewed-by:
Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-6-jithu.joseph@intel.comReviewed-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Jithu Joseph authored
Define MSR bitfields for enumerating support for Array BIST test. Signed-off-by:
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Jithu Joseph authored
Cleanup incorporating misc review comments - Remove the subdirectory intel_ifs/0 for devicenode [1] - Make plat_ifs_groups non static and use it directly without using a function [2] Link: https://lore.kernel.org/lkml/Y+4kQOtrHt5pdsSO@kroah.com/ [1] Link: https://lore.kernel.org/lkml/Y9nyxNesVHCUXAcH@kroah.com/ [2] Signed-off-by: -
Jithu Joseph authored
The struct holding device driver data contained both read only(ro) and read write(rw) fields. Separating ro fields from rw fields was recommended as a preferable design pattern during review[1]. Group ro fields into a separate const struct. Associate it to the miscdevice being registered by keeping its pointer in the same container struct as the miscdevice. Link: https://lore.kernel.org/lkml/Y+9H9otxLYPqMkUh@kroah.com/ [1] Signed-off-by:
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Jithu Joseph authored
In preparation to supporting additional tests, remove ifs_pkg_auth from per-test scope, as it is only applicable for one test type. This will simplify ifs_init() flow when multiple tests are added. Signed-off-by:
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Nikita Kravets authored
Add a new driver to allow various MSI laptops' functionalities to be controlled from userspace. This includes such features as power profiles (aka shift modes), fan speed, charge thresholds, LEDs, etc. This driver contains EC memory configurations for different firmware versions and exports battery charge thresholds to userspace (note, that start and end thresholds control the same EC parameter and are always 10% apart). Link: https://github.com/BeardOverflow/msi-ec/ Link: https://github.com/BeardOverflow/msi-ec/pull/13 Cc: Aakash Singh <mail@singhaakash.dev> Cc: Jose Angel Pastrana <japp0005@red.ujaen.es> Signed-off-by:
Nikita Kravets <teackot@gmail.com> Link: https://lore.kernel.org/r/20230320225509.3559-1-teackot@gmail.comReviewed-by:
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Hans de Goede authored
Summary of changes: Till the commit: "tools/power/x86/intel-speed-select: Get punit core mapping information" All patches just lays foundation for adding new hardware interface in addition to existing MSR/MMIO interface. All patches prefixed with "Abstract" just adds individual hardware callback for functions called from the core processing. The mailbox processing is abstracted to a new file with callbacks. In addition some changes to reduce duplicated code for display of TRL level. Patch "Introduce Punit ID concept and add related API" add further abstraction in addition to existing package and die scope. ----------- tools/power/x86/intel-speed-select: Get punit core mapping information -Adds a new way to get package/die/punit information for each CPU. ----------- Introduce TPMI interface support - Implement all abstracted callbacks above to use TPMI IOCTL interface. ----------- tools/power/x86/intel-speed-select: Display punit info - With TPMI the granularity is per punit, which can be multiple in a package/die. ---------- tools/power/x86/intel-speed-select: Remove cpu mask display for non-cpu power domain tools/power/x86/intel-speed-select: Display fact info for non-cpu power domain -There are some power domains with no CPUs, the above patches adds CPU as invalid for these domains ---------- tools/power/x86/intel-speed-select: Use cgroup v2 isolation - Adds new option to use Cgroup CPU isolation instead of offline of CPUs ---------- tools/power/x86/intel-speed-select: Change TRL display for Emerald Rapids - Emerald Rapid has multiple TRL levels and moves away from TRL level based on instruction type
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- 22 Mar, 2023 33 commits
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Zhang Rui authored
Update tool and supported API version. This is the first version which supports newer Xeon platforms with TPMI support. Signed-off-by:
Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: subject and changelog edits] Signed-off-by:
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
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Srinivas Pandruvada authored
Emerald Rapids doesn't specify TRL (Turbo Ratio Limits) based instruction types. Instead it specifies 5 TRL levels, which can be anyone of the instruction types. Increase TRL levels to 5 for Emerald Rapids. Also change display to show by level number. Show only non zero level values. Signed-off-by: -
Srinivas Pandruvada authored
There are some differences compared to Sapphire Rapids. So, add a separate API. Signed-off-by: -
Srinivas Pandruvada authored
AMX frequency is present in non TPMI platforms also. When platform supports, the value is non zero. So, display AMX base frequency when non zero, irrespective of platform API version. Signed-off-by: -
Srinivas Pandruvada authored
On supported systems, it is possiible to isolate CPUs instead of CPU online/offline. This is optional and can be specified using -g option when running as daemon or in combination with -o option for SST-PP level change. CPU isolation doesn't isolate IRQs. So IRQs needs to be moved away from isoolated CPUs. This can be done via IRQ sysfs or irqbalance daemon. The IRQ balance daemon is also capable to parse thermal HFI messages to move IRQs away from CPUS, which are supposed be isolated. But this requires version released after July 2022. Signed-off-by: -
Srinivas Pandruvada authored
During perf level change cpuset is allocated but not freed. Add free_cpu_set() in success and failure path. Although this is not an issue, as the program will exit after processing of online/offline, but for completeness add the free_cpu_set(). Signed-off-by: -
Zhang Rui authored
Comparing clos_config->clos_max with 255 is broken with TPMI I/F because of different isst_get_disp_freq_multiplier() used. Checking for clos_config->clos_max * isst_get_disp_freq_multiplier() instead. Signed-off-by:
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Zhang Rui authored
Some operations applies to cpu-power-domain only. Add check for cpu id for these functions. Signed-off-by:
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Zhang Rui authored
If the new TDP level requetsted is same as the current TDP level, don't call into driver to change level. Signed-off-by:
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Zhang Rui authored
Non CPU power domains will not have any CPUs. So don't display any CPU count or enable mask. Signed-off-by:
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Zhang Rui authored
TRL levels with Zero ratio values is meaningless. Prevent these TRL levels from being displayed. Signed-off-by:
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Zhang Rui authored
Allow displaying SST-TF info for non-cpu power domain. Signed-off-by:
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Zhang Rui authored
level 0 name is not shown in some case for backward compatibility reason. No need to keep this quirk for new api_version. Signed-off-by:
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Zhang Rui authored
Non-cpu power domain does not support cpu clos config. Signed-off-by:
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Zhang Rui authored
Some power domain may not have CPUs associated, allow displaying information for these non-cpu power domains. Signed-off-by:
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Zhang Rui authored
amx_p1 and cooling_type are newly introduced for TPMI interface. Display amx_p1 and cooling_type info for platforms that support them. Signed-off-by:
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Zhang Rui authored
Display punit info for platforms with new api_version. For platforms with old api_version, don't display the punit info to be backward compatible. For example: Intel(R) Speed Select Technology Executing on CPU model:173[0xad] package-0 die-0 powerdomain-0 cpu-0 get-config-current_level:0 package-0 die-0 powerdomain-3 cpu--1 get-config-current_level:0 package-0 die-0 powerdomain-4 cpu--1 get-config-current_level:0 Signed-off-by: -
Zhang Rui authored
TPMI (Topology Aware Register and PM Capsule Interface) creates a flexible, extendable and software-PCIe-driver-enumerable MMIO interface for PM features. SST feature is exposed via the TPMI interface on newer Xeon platforms. Kernel TPMI based SST driver provides a series of new IOCTLs for userspace to use. Introduce support for the platforms that do SST control via TPMI interface. Compared with previous platforms, Newer Xeons also supports multi-punit in a package/die, including cpu punit and non-cpu punit. These have already been handled in the generic code. Signed-off-by:
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Srinivas Pandruvada authored
Get punit core mapping information using format of MSR 0x54. Based on the API version, decode is done using new format. The new format also include a power domain ID. TPMI SST information is for each power domain. Signed-off-by: -
Zhang Rui authored
In some cases, the output format may be different with different api_version because of different capabilities or for backward capabilities reason. Introduce api_version() to get the api_version of the platform running. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
clos_min/max in TPMI interface is frequency in MHz, thus clos_min/max needs to support larger values. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Platform specific code also needs to give debug output. Introduce is_debug_enabled() for this purpose. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Different api_version suggests different kernel driver used and different interface is used to communication with the hardware. Allow setting platform specific callbacks based on api_version. Currently, all platforms with api_version 1 uses Mbox/MMIO interfaces. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
After the previous cleanup, there is no user of send_mbox_cmd outside of isst-core-mbox.c. Thus move send_mbox_cmd to isst-core-mbox.c as internal functions. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to adjust the uncore frequency. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to get SST-CP capability and current state. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to set per core CLOS setting. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to get per core CLOS setting. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to set CLOS priority setting. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to get CLOS priority setting. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to set CLOS config settings. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to get CLOS config setting. No functional changes are expected. Signed-off-by:
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Zhang Rui authored
Allow platform specific implementation to get turbo ratio limits of each AVX level, for a selected SST-PP level. No functional changes are expected. Signed-off-by:
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