- 17 Sep, 2015 1 commit
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Gabriel Fernandez authored
Use a generic name for this kind of PLL Correction in dts files are already done here: commit 5eb26c60 ("ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x") Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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- 16 Sep, 2015 2 commits
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Mans Rullgard authored
If a mux clock is initialised (by hardware or firmware) with an invalid parent, its ->get_parent() can return an out of range index. For example, the generic mux clock attempts to return -EINVAL, which due to the u8 return type ends up a rather large number. Using this index with the parent_names[] array results in an invalid pointer and (usually) a crash in the following strcmp(). This patch adds a check for the parent index being in range, ignoring clocks reporting invalid values. Signed-off-by:
Mans Rullgard <mans@mansr.com> Tested-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
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Thierry Reding authored
The OPP list needs to be protected against concurrent accesses. Using simple RCU read locks does the trick and gets rid of the following lockdep warning: =============================== [ INFO: suspicious RCU usage. ] 4.2.0-next-20150908 #1 Not tainted ------------------------------- drivers/base/power/opp.c:460 Missing rcu_read_lock() or dev_opp_list_lock protection! other info that might help us debug this: rcu_scheduler_active = 1, debug_locks = 0 4 locks held by kworker/u8:0/6: #0: ("%s""deferwq"){++++.+}, at: [<c0040d8c>] process_one_work+0x118/0x4bc #1: (deferred_probe_work){+.+.+.}, at: [<c0040d8c>] process_one_work+0x118/0x4bc #2: (&dev->mutex){......}, at: [<c03b8194>] __device_attach+0x20/0x118 #3: (prepare_lock){+.+...}, at: [<c054bc08>] clk_prepare_lock+0x10/0xf8 stack backtrace: CPU: 2 PID: 6 Comm: kworker/u8:0 Not tainted 4.2.0-next-20150908 #1 Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) Workqueue: deferwq deferred_probe_work_func [<c001802c>] (unwind_backtrace) from [<c00135a4>] (show_stack+0x10/0x14) [<c00135a4>] (show_stack) from [<c02a8418>] (dump_stack+0x94/0xd4) [<c02a8418>] (dump_stack) from [<c03c6f6c>] (dev_pm_opp_find_freq_ceil+0x108/0x114) [<c03c6f6c>] (dev_pm_opp_find_freq_ceil) from [<c0551a3c>] (dfll_calculate_rate_request+0xb8/0x170) [<c0551a3c>] (dfll_calculate_rate_request) from [<c0551b10>] (dfll_clk_round_rate+0x1c/0x2c) [<c0551b10>] (dfll_clk_round_rate) from [<c054de2c>] (clk_calc_new_rates+0x1b8/0x228) [<c054de2c>] (clk_calc_new_rates) from [<c054e44c>] (clk_core_set_rate_nolock+0x44/0xac) [<c054e44c>] (clk_core_set_rate_nolock) from [<c054e4d8>] (clk_set_rate+0x24/0x34) [<c054e4d8>] (clk_set_rate) from [<c0512460>] (tegra124_cpufreq_probe+0x120/0x230) [<c0512460>] (tegra124_cpufreq_probe) from [<c03b9cbc>] (platform_drv_probe+0x44/0xac) [<c03b9cbc>] (platform_drv_probe) from [<c03b84c8>] (driver_probe_device+0x218/0x304) [<c03b84c8>] (driver_probe_device) from [<c03b69b0>] (bus_for_each_drv+0x60/0x94) [<c03b69b0>] (bus_for_each_drv) from [<c03b8228>] (__device_attach+0xb4/0x118) ata1: SATA link down (SStatus 0 SControl 300) [<c03b8228>] (__device_attach) from [<c03b77c8>] (bus_probe_device+0x88/0x90) [<c03b77c8>] (bus_probe_device) from [<c03b7be8>] (deferred_probe_work_func+0x58/0x8c) [<c03b7be8>] (deferred_probe_work_func) from [<c0040dfc>] (process_one_work+0x188/0x4bc) [<c0040dfc>] (process_one_work) from [<c004117c>] (worker_thread+0x4c/0x4f4) [<c004117c>] (worker_thread) from [<c0047230>] (kthread+0xe4/0xf8) [<c0047230>] (kthread) from [<c000f7d0>] (ret_from_fork+0x14/0x24) Signed-off-by:Thierry Reding <treding@nvidia.com> Fixes: c4fe70ad ("clk: tegra: Add closed loop support for the DFLL") [vince.h@nvidia.com: Unlock rcu on error path] Signed-off-by:
Vince Hsu <vince.h@nvidia.com> [sboyd@codeaurora.org: Dropped second hunk that nested the rcu read lock unnecessarily] Signed-off-by:
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- 14 Sep, 2015 1 commit
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Heiko Stübner authored
Again a result of the gpio-clock-liberation the rk3368 needs the pclk_pd_pmu marked as critical, to boot successfully. Reported-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
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- 10 Sep, 2015 3 commits
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Romain Perier authored
Now that the rockchip clock subsystem does clock gating with GPIO banks, these are no longer enabled once during probe and no longer stay enabled for eternity. When all these clocks are disabled, the parent clock pclk_peri might be disabled too, as no other child claims it. So, we need to add pclk_peri to the critical clocks. Signed-off-by:
Romain Perier <romain.perier@gmail.com> Tested-by:
Michael Niewoehner <linux@mniewoehner.de> Signed-off-by:
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Michael Niewoehner authored
pclk_cpu needs to keep running because it is needed for devices like the act8865 regulator but with the recent gpio clock handling this is not always the case anymore. So add it to the list of critical clocks. Signed-off-by:
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Heiko Stuebner authored
Currently the registration of critical clocks is done in the function shared between rk3066 and rk3188 clock trees. That results in them getting handled maybe before all of them are registered. Therefore move the critical clock handling down to the end of the soc- specific clock registration function, so that all clocks are registered before they're maybe handled as critical clock. Signed-off-by:
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- 03 Sep, 2015 2 commits
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Leo Yan authored
The previous code, kernel builds Hi6220's common clock driver and stub clock driver together. Stub clock driver has introduced the dependency with CONFIG_MAILBOX, so kernel will not build Hi6220's common clock driver due ARM64's defconfig have not enabled CONFIG_MAILBOX by default. So separately build stub clock driver and common clock driver for Hi6220; and only let stub clock driver has the dependency with CONFIG_MAILBOX. Signed-off-by:
Leo Yan <leo.yan@linaro.org> Tested-by:
Kevin Hilman <khilman@linaro.org> Signed-off-by:
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Guenter Roeck authored
Recent cleanup removed some include files without checking if the cleaned up code still compiles. This results in the following compile error. drivers/clk/h8300/clk-h8s2678.c: In function ‘h8s2678_pll_clk_setup’: drivers/clk/h8300/clk-h8s2678.c:99:14: error: implicit declaration of function ‘kzalloc’ drivers/clk/h8300/clk-h8s2678.c:138:2: error: implicit declaration of function ‘kfree’ Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by:Guenter Roeck <linux@roeck-us.net> Signed-off-by:
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- 27 Aug, 2015 1 commit
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Marek Szyprowski authored
Commit d5e136a2 ("clk: samsung: Register clk provider only after registering its all clocks", merged to v3.17-rc1) modified a way that driver registers registers to core framework. This change has not been applied to s5pv210 clocks driver, which has been merged in parallel to that commit. This patch adds a missing call to samsung_clk_of_add_provider(), so the driver is operational again. Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> CC: stable@vger.kernel.org # v3.17+ Acked-by:
Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
Michael Turquette <mturquette@baylibre.com>
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- 26 Aug, 2015 4 commits
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Damien.Horsley authored
Current critical clock list for pistachio enables only mips and sys clocks by default but there are also other clocks that are not claimed by anyone and needs to be enabled by default. This patch updates the critical clocks that need to be enabled by default. Add a separate struct to distinguish the critical clocks as listed: 1.) core clocks: a.) mips clock 2.) peripheral system clocks: a.) sys clock b.) sys_bus clock c.) DDR clock d.) ROM clock Fixes: b35d7c33("CLK: Pistachio: Register core clocks") Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by:
Damien.Horsley <Damien.Horsley@imgtec.com> Signed-off-by:
Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by:
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Zdenko Pulitika authored
.recalc_rate callback for the fractional PLL doesn't take operating mode into account when calculating PLL rate. This results in the incorrect PLL rates when PLL is operating in integer mode. Operating mode of fractional PLL is based on the value of the fractional divider. Currently it assumes that the PLL will always be configured in fractional mode which may not be the case. This may result in the wrong output frequency. Also vco was calculated based on the current operating mode which makes no sense because .set_rate is setting operating mode. Instead, vco should be calculated using PLL settings that are about to be set. Fixes: 43049b0c("CLK: Pistachio: Add PLL driver") Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by:
Zdenko Pulitika <zdenko.pulitika@imgtec.com> Signed-off-by:
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Zdenko Pulitika authored
PLL enable callbacks are overriding PLL mode (int/frac) and Noise reduction (on/off) settings set by the boot loader which results in the incorrect clock rate. PLL mode and noise reduction are defined by the DSMPD and DACPD bits of the PLL control register. PLL .enable() callbacks enable PLL by deasserting all power-down bits of the PLL control register, including DSMPD and DACPD bits, which is not necessary since these bits don't actually enable/disable PLL. This commit fixes the problem by removing DSMPD and DACPD bits from the "PLL enable" mask. Fixes: 43049b0c("CLK: Pistachio: Add PLL driver") Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by:
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Zdenko Pulitika authored
This commit fixes 32bit integer overflows throughout the pll driver (i.e. wherever the result of integer multiplication may exceed the range of u32). One of the functions affected by this problem is .recalc_rate. It returns incorrect rate for some pll settings (not for all though) which in turn results in the incorrect rate setup of pll's child clocks. Fixes: 43049b0c("CLK: Pistachio: Add PLL driver") Cc: <stable@vger.kernel.org> # 4.1 Reviewed-by:
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- 25 Aug, 2015 4 commits
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Stephen Boyd authored
The latest Tegra clk pull had some problems. Fix them. drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static? drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static? drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero. Signed-off-by: -
Stephen Boyd authored
Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.3-rc1 This contains the DFLL driver needed to implement CPU frequency scaling on Tegra.
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Georgi Djakov authored
Fix the enable bit of the pseudorandom number generator clock. Reported-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Fixes: 3966fab8 "clk: qcom: Add MSM8916 Global Clock Controller support" Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by:
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Chen-Yu Tsai authored
of_clk_set_defaults uses the type 'bool', but clk-conf.h does not include its definition. This results in a compile error when only clk-conf.h is used. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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- 24 Aug, 2015 22 commits
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Nicolas Pitre authored
Init data marked const should be annotated with __initconst for correctness and not __initdata. This also fixes LTO builds that otherwise fail with section mismatch errors. Signed-off-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
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Heiko Stuebner authored
The structure is xin24m -> pll -> pll-mux (xin24m,pll,xin32k). The pll does have an init callback to make sure the boot-selected frequency is using the expected pll settings and resets the same frequency using the values provided in the driver if necessary. The setting itself also involves remuxing the pll-mux temporarily to the xin24m source to let the new pll rate settle. Until now this worked flawlessly, even when it had the flaw of accessing the mux settings before the mux actually got registered. With the recent clock-core conversions this flaw became apparent in null pointer dereference in [<c03fc400>] (clk_hw_get_num_parents) from [<c0400df0>] (clk_mux_get_parent+0x14/0xc8) [<c0400ddc>] (clk_mux_get_parent) from [<c040246c>] (rockchip_rk3066_pll_set_rate+0xd8/0x320) So to fix that, simply register the pll-mux before the pll, so that it will be fully initialized when the pll clock executes its init- callback and possibly touches the pll-mux clock. Signed-off-by:
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Linus Walleij authored
These Ux500 clocks have been around for years and were never properly documented. Add the proper binding documentation. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
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Linus Walleij authored
The base addresses for the Ux500 PRCC controllers are hardcoded, let's move them to the clock node in the device tree and delete the constants. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net> Acked-by:
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Dong Aisheng authored
__clk_set_parent_after() actually used the second argument then we could put this duplicate logic in there and call it with a different order of arguments in the success vs. error paths in this function. Cc: Mike Turquette <mturquette@linaro.org> Suggested-by:
Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by:
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Stephen Boyd authored
Use the provider based method to get a clock's name so that we can get rid of the clk member in struct clk_hw one day. Mostly converted with the following coccinelle script. @@ struct clk_hw *E; @@ -__clk_get_name(E->clk) +clk_hw_get_name(E) Acked-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be> Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by:
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Stephen Boyd authored
We don't modify the clk_hw argument in these functions, so it's safe to mark it as const. Signed-off-by: -
Leo Yan authored
On Hi6220, there have some clocks which can use mailbox channel to send messages to power controller to change frequency; this includes CPU, GPU and DDR clocks. For dynamic frequency scaling, firstly need write the frequency value to SRAM region, and then send message to mailbox to trigger power controller to handle this requirement. This driver will use syscon APIs to pass SRAM memory region and use common mailbox APIs for channels accessing. This init driver will support cpu frequency change firstly. Signed-off-by:
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Leo Yan authored
Document the new compatible for stub clock driver which is used for CPU and DDR's dynamic frequency scaling. Signed-off-by:
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Leo Yan authored
Document "hisilicon,hi6220-sramctrl" for SRAM controller. Signed-off-by:
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Guo Zeng authored
PLL VCO frequency is given by Fvco = Fref * 2 * NF / NR in integer-N mode, or by Fvco = Fref * SSN / NR in Spread Spectrum (fractional-N) mode. Thus fix the missing part of NR Signed-off-by:
Guo Zeng <guo.zeng@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Guo Zeng authored
bit4 thcpum_cpudiv4_clken r/w thcpum_cpudiv4_clk clock enable (default: 1) Root clock CPU_CLK must be enabled for this clock to be enabled bit3 coresight_tpiu_clken r/w coresight_tpiu_clk clock enable (default: 0) Root clock TPIU_CLK must be enabled for this clock to be enabled Signed-off-by:
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Yibo Cai authored
Signed-off-by:
Yibo Cai <yibo.cai@csr.com> Signed-off-by:
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Yibo Cai authored
I cannot believe that I spend quite a lot time in finding this bug. It seems a pitfall people tend to fall in. In "int64 = int32 * int32", conversion from 32-bits to 64-bits comes after the multiplication. So this statement may not work as expected. Signed-off-by:
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Guo Zeng authored
this patch makes mux clks can be referenced by device drivers. Signed-off-by:
Barry Song <Barry.Song@csr.com> Signed-off-by:
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Guo Zeng authored
Signed-off-by:
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Dinh Nguyen authored
The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by:
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Linus Walleij authored
This code is unused and not coming back. Let's kill it off. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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Stephen Boyd authored
Remove these APIs now that we've converted all users to the replacement struct clk_hw based versions. Signed-off-by: -
Stephen Boyd authored
This driver uses __clk_get_name() when it's dealing with struct clk_hw pointers. Use the simpler form so that we can get rid of the clk member in struct clk_hw one day. Acked-by:
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Stephen Boyd authored
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Cc: Wentao Xu <wentaox@codeaurora.org> Cc: Rob Clark <robdclark@gmail.com> Signed-off-by: -
Stephen Boyd authored
We're removing struct clk from the clk provider API. This code is calling the consumer APIs to change the parent to a 1 MHz fixed rate clock for each of the clocks that the driver provides. Move to using the assigned-clock-parents DT property for this instead. Because this is an ABI break, detect if the property is missing and fall back to setting the parent explicitly before the clocks are registered. Acked-by:
Pawel Moll <pawel.moll@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Tested-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
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