- 28 Sep, 2022 1 commit
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Rajendra Nayak authored
GDSCs cannot be transitioned into a Retention state in SW. When either the RETAIN_MEM bit, or both the RETAIN_MEM and RETAIN_PERIPH bits are set, and the GDSC is left ON, the HW takes care of retaining the memory/logic for the domain when the parent domain transitions to power collapse/power off state. On some platforms where the parent domains lowest power state itself is Retention, just leaving the GDSC in ON (without any RETAIN_MEM/RETAIN_PERIPH bits being set) will also transition it to Retention. The existing logic handling the PWRSTS_RET seems to set the RETAIN_MEM/RETAIN_PERIPH bits if the cxcs offsets are specified but then explicitly turns the GDSC OFF as part of _gdsc_disable(). Fix that by leaving the GDSC in ON state. Signed-off-by:
Rajendra Nayak <quic_rjendra@quicinc.com> Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920111517.10407-1-quic_rjendra@quicinc.com
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- 27 Sep, 2022 25 commits
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Bjorn Andersson authored
Add driver for the GPU clock controller in the Qualcomm SC8280XP platform. Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> [bjorn: Included kernel.h and lower-cased hex numbers] Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Add compatible for the Qualcomm SC8280XP GPU. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Konrad Dybcio authored
Add support for controlling SMD RPM clocks on SM6375. Signed-off-by:
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Konrad Dybcio authored
Add the missing definition for the aforementioned clock. Signed-off-by:
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Konrad Dybcio authored
Add a compatible for RPMCC on SM6375. Signed-off-by:
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Richard Acayan authored
The Snapdragon 670 uses the RPMh mailbox for most of the clocks used in SDM845 but omits two. Add clock data for SDM670 so the driver doesn't fail to resolve a clock. Link: https://android.googlesource.com/kernel/msm/+/443bd8d6e2cf54698234c752e6de97b4b8a528bd%5E%21/#F7Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Richard Acayan authored
The Snapdragon 670 uses the RPMh mailbox for some clocks. Document its support. Signed-off-by:
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Krzysztof Kozlowski authored
Emails to codeaurora.org bounce ("Recipient address rejected: undeliverable address: No such user here."). Signed-off-by:Rob Herring <robh@kernel.org> Signed-off-by:
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Iskren Chernev authored
The qcom2260 and sm6115 GCC drivers use a common modified DEFAULT and BRAMMO alpha pll offsets. Move these common offsets to the shared place to avoid duplication. The new layouts have a suffix EVO similar to LUCID and RIVIAN. Signed-off-by:
Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by:
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Iskren Chernev authored
sm6115 uses a modified default and bramo alpha pll offsets. Put them in the same place for consistency. Signed-off-by:
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Adam Skladowski authored
The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but currently only BRAMMO ones are overridden. Override DEFAULT ones too. A very similar thing is happening in gcc-qcm2290 driver. Fixes: cbe63bfd ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by:
Adam Skladowski <a_skl39@protonmail.com> Signed-off-by:
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Dmitry Baryshkov authored
Add support for the dispcc on Qualcomm SM8450 platform. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Dmitry Baryshkov authored
PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by:
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Dmitry Baryshkov authored
Add device tree bindings for the display clock controller on Qualcomm SM8450 platform. Signed-off-by:
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Adam Skladowski authored
Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Signed-off-by:
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Adam Skladowski authored
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6115 SoC. Signed-off-by:
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Krishna chaitanya chundru authored
Enabling PCIe GDSC retention to ensure controller and its dependent clocks won't go down during system suspend. Update the .pwrsts for PCIe GDSC so it only transitions to RET in low power. Signed-off-by:
Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by:
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Satya Priya authored
Change the qcom_cc_probe_by_index() call to qcom_cc_really_probe() to avoid remapping of memory region for index 0, which is already being done through qcom_cc_map(). Fixes: 7c6a6641 ("clk: qcom: lpass: Add support for resets & external mclk for SC7280") Signed-off-by:
Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by:
Neil Armstrong <neil.armstrong@baylibre.com> Signed-off-by:
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Robert Marko authored
Add support for IPQ8074 since it uses the same PLL setup, however it uses slightly different Alpha PLL config. Alpha PLL config was obtained by dumping PLL registers from a running device. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Robert Marko authored
Update the IPQ6018 Alpha PLL config to the latest one from the downstream 5.4 kernel[1]. This one should match the production SoC-s. Tested on IPQ6018 CP01-C1 reference board. [1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41Signed-off-by:
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Robert Marko authored
Convert the driver to use OF match data for providing the Alpha PLL config per compatible. This is required for IPQ8074 support since it uses a different Alpha PLL config. While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make it clear that it is for IPQ6018 only. Signed-off-by:
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Robert Marko authored
Add IPQ8074 compatible to A53 PLL bindings. Signed-off-by:
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Robert Marko authored
While fixing up the driver I noticed that my IPQ8074 board was hanging after CPUFreq switched the frequency during boot, WDT would eventually reset it. So mark apcs_alias0_core_clk as critical since its the clock feeding the CPU cluster and must never be disabled. Fixes: 5e77b4ef ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by:
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Robert Marko authored
While working on IPQ8074 APSS driver it was discovered that IPQ6018 and IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is currently broken. More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux clock. However after debugging why it was always stuck at 800Mhz, it was figured out that its not regmap_mux compatible at all. It is a simple mux but it uses RCG2 register layout and control bits, so utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not having to provide a dummy frequency table. While we are here, use ARRAY_SIZE for number of parents. Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards. Fixes: 5e77b4ef ("clk: qcom: Add ipq6018 apss clock controller") Signed-off-by:
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Christian Marangi authored
An RCG may act as a mux that switch between 2 parents. This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds the CPU cluster clock just switches between XO and the PLL that feeds it. Add the required ops to add support for this special configuration and use the generic mux function to determine the rate. This way we dont have to keep a essentially dummy frequency table to use RCG2 as a mux. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
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- 26 Sep, 2022 14 commits
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Christian Marangi authored
Use ARRAY_SIZE for num_parents instead of raw number to prevent any confusion/mistake. Signed-off-by:
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Christian Marangi authored
Convert lcc-ipq806x driver to parent_data API. Change parent_name for pll4 to pxo_board to prepare the future to eventually drop the double pxo board clk. Signed-off-by:
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Christian Marangi authored
Add reset definition for lcc-ipq806x. Signed-off-by:
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Christian Marangi authored
Add pcm reset define for ipq806x lcc. Signed-off-by:
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Dmitry Baryshkov authored
Both pmux instances share the same width and shift. Specify the mask at compile time to simplify functions. Signed-off-by:
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Dmitry Baryshkov authored
Don't store pointers to parents in struct clk_cpu_8996_pmux. Instead use clk_hw_get_parent_by_index to fetch them. Signed-off-by:
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Dmitry Baryshkov authored
Rather than telling everybody that we are using PLL as a parent (and using ACD clock instead) properly select ACD as a pmux parent clock. Signed-off-by:
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Dmitry Baryshkov authored
To simplify the code, define 1:1 fixed factor clocks to represent the ACD pmux parent. Signed-off-by:
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Dmitry Baryshkov authored
Switch to using devres-managed version of clk_notifier_register(). This allows us to drop driver's remove() callback. Signed-off-by:
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Yassine Oudjana authored
Replace parent_names in PLLs, secondary muxes and primary muxes with parent_data. For primary muxes there were never any *cl_pll_acd clocks, so instead of adding them, put the primary PLLs in both PLL_INDEX and ACD_INDEX, then make sure ACD_INDEX is always picked over PLL_INDEX when setting parent since we always want ACD when using the primary PLLs. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> [DB: switch to parent_hws for pmux clocks] Signed-off-by:
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Yassine Oudjana authored
The clocks currently listed in clocks and clock-names are the ones supplied by this clock controller, not the ones it consumes. Replace them with the only clock it consumes - the on-board oscillator (XO), and make the properties required. Signed-off-by:
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Yassine Oudjana authored
There is nothing special about the secondary muxes, unlike the primary muxes which need some extra logic to handle ACD and switching between primary PLL and secondary mux sources. Turn them into clk_regmap_mux and rename cpu_clk_msm8996_mux into cpu_clk_msm8996_pmux to make it specific to primary muxes. Signed-off-by:
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Yassine Oudjana authored
The power cluster comes before the performance cluster. Make everything in the driver follow this order. Signed-off-by:
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Yassine Oudjana authored
This will allow for adding them to clk_parent_data arrays in an upcoming patch. Signed-off-by:
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