- 30 Sep, 2022 5 commits
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Fabien Parent authored
Add clock drivers for MT8365 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Signed-off-by:
Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.comReported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Markus Schneider-Pargmann authored
To make clk-mt8365 compilable as a module there are a few function symbols missing. This patch adds the required EXPORT_SYMBOL_GPL to the functions. Signed-off-by:
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Markus Schneider-Pargmann authored
Provide a helper that replaces the kzalloc with devm_kzalloc so error handling gets easier. Signed-off-by:
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Fabien Parent authored
Add the clock bindings for the MediaTek MT8365 SoC. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Stephen Boyd authored
Merge tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux into clk-mtk Pull MediaTek clk driver updates from Chen-Yu Tsai: A lot of clean up work, as well as new drivers and new functions - New clock drivers for MediaTek Helio X10 MT6795 - Add missing DPI1_HDMI clock in MT8195 VDOSYS1 - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195 - Fix GPU clock topology on MT8195 - Propogate rate changes from GPU clock gate up the tree - Clock mux notifiers for GPU-related PLLs - Conversion of more "simple" drivers to mtk_clk_simple_probe() - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers - Fixes to previous |struct clk| to |struct clk_hw| conversion - Shrink MT8192 clock driver by deduplicating clock parent lists * tag 'mtk-clk-for-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux: (31 commits) clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks clk: mediatek: mt8192: add mtk_clk_simple_remove clk: mediatek: mt8183: use mtk_clk_simple_probe to simplify driver clk: mediatek: mt6797: use mtk_clk_simple_probe to simplify driver clk: mediatek: mt6779: use mtk_clk_simple_probe to simplify driver ...
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- 29 Sep, 2022 12 commits
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Chen-Yu Tsai authored
Some groups of clocks of the same type share the same list of parents. These lists were declared separately for each clock in older drivers, bloating the code. Merge some obvious duplicate parent clock lists in the MT8192 clock driver together to reduce the code size. These include: - apll_i2s*_m_parents into one as apll_i2s_m_parents - img1_parents & img2_parents into one as img_parents - msdc30_*_parents into one as msdc30_parents - camtg*_parents into cam_tg_parents - seninf*_parents into seninf_parents Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220926102523.2367530-6-wenst@chromium.orgSigned-off-by:
Chen-Yu Tsai <wenst@chromium.org>
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Chen-Yu Tsai authored
During the previous |struct clk| to |struct clk_hw| clk provider API migration in commit 6f691a58 ("clk: mediatek: Switch to clk_hw provider APIs"), a few clk_unregister_*() calls were missed. Migrate the remaining ones to the |struct clk_hw| provider API, i.e. change clk_unregister_*() to clk_hw_unregister_*(). Fixes: 6f691a58 ("clk: mediatek: Switch to clk_hw provider APIs") Reviewed-by:
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Chen-Yu Tsai authored
When the cleanup paths for the various clk register APIs in the MediaTek clk library were added, the one in the dividers type used the wrong type of unregister function. This would result in incorrect dereferencing of the clk pointer and freeing of invalid pointers. Fix this by switching to the correct type of clk unregistration call. Fixes: 3c3ba2ab ("clk: mediatek: mtk: Implement error handling in register APIs") Reviewed-by:
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AngeloGioacchino Del Regno authored
Following the changes that were done for mt8183, add a clock notifier for the GPU PLL selector mux: this allows safe clock rate changes by temporarily reparenting the GPU to a safe clock (clk26m) while the MFGPLL is reprogrammed and stabilizes. Signed-off-by:
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AngeloGioacchino Del Regno authored
Following what was done on MT8183 and MT8195, also propagate the rate changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS. Signed-off-by:
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AngeloGioacchino Del Regno authored
These PLLs are conflicting with GPU rates that can be generated by the GPU-dedicated MFGPLL and would require a special clock handler to be used, for very little and ignorable power consumption benefits. Also, we're in any case unable to set the rate of these PLLs to something else that is sensible for this task, so simply drop them: this will make the GPU to be clocked exclusively from MFGPLL for "fast" rates, while still achieving the right "safe" rate during PLL frequency locking. Signed-off-by:
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AngeloGioacchino Del Regno authored
Following the changes done to MT8183, register a similar notifier for MT8195 as well, allowing safe clockrate updates for the MFGPLL. Signed-off-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220927101128.44758-8-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
This clock was being registered as clk-composite through the helpers for the same in the MediaTek clock APIs but, in reality, this isn't a composite clock. Appropriately register this clock with devm_clk_hw_register_mux(). No functional changes. Signed-off-by:
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AngeloGioacchino Del Regno authored
The MFG_BG3D is a gate to enable/disable clock output to the GPU, but the actual output is decided by multiple muxes; in particular: mfg_ck_fast_ref muxes between "slow" (top_mfg_core_tmp) and "fast" (MFGPLL) clock, while top_mfg_core_tmp muxes between the 26MHz clock and various system PLLs. The clock gate comes after all the muxes, so its parent is mfg_ck_fast_reg, not top_mfg_core_tmp. Reparent MFG_BG3D to the latter to match the hardware and add the CLK_SET_RATE_PARENT flag to it: this way we ensure propagating rate changes that are requested on MFG_BG3D along its entire clock tree. Fixes: 35016f10 ("clk: mediatek: Add MT8195 mfgcfg clock support") Signed-off-by:
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Chen-Yu Tsai authored
When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by:
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Chen-Yu Tsai authored
With device frequency scaling, the mux clock that (indirectly) feeds the device selects between a dedicated PLL, and some other stable clocks. When a clk rate change is requested, the (normally) upstream PLL is reconfigured. It's possible for the clock output of the PLL to become unstable during this process. To avoid causing the device to glitch, the mux should temporarily be switched over to another "stable" clock during the PLL rate change. This is done with clk notifiers. This patch adds common functions for notifiers to temporarily and transparently reparent mux clocks. This was loosely based on commit 8adfb086 ("clk: sunxi-ng: mux: Add clk notifier functions"). Signed-off-by:
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Chen-Yu Tsai authored
The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its rate change requests to its parent, so that DVFS for the GPU can work properly. Fixes: acddfc2c ("clk: mediatek: Add MT8183 clock support") Signed-off-by:
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- 26 Sep, 2022 19 commits
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Yassine Oudjana authored
Register gates with dev in mtk_clk_simple_probe. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by:
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Yassine Oudjana authored
This allows it to be used in drivers built as modules. Signed-off-by:
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Pablo Sun authored
Add the clock gate definition for the DPI1 hardware in VDOSYS1. The parent clock "hdmi_txpll" is already defined in `mt8195.dtsi`. Signed-off-by:
Pablo Sun <pablo.sun@mediatek.com> Signed-off-by:
Guillaume Ranquet <granquet@baylibre.com> Reviewed-by:
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Pablo Sun authored
Expand dt-bindings slot for VDOSYS1 of MT8195. This clock is required by the DPI1 hardware and is a downstream of the HDMI pixel clock. Signed-off-by:
Mattijs Korpershoek <mkorpershoek@baylibre.com> Acked-by:
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Miles Chen authored
mt8192 is already using mtk_clk_simple_probe, but not mtk_clk_simple_remove. Let's add mtk_clk_simple_remove for mt8192. Signed-off-by:
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Miles Chen authored
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by:
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Miles Chen authored
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by:
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Miles Chen authored
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by:
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Miles Chen authored
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by:
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Miles Chen authored
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by:
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Miles Chen authored
mtk_clk_simple_probe was added by Chun-Jie to simply common flow of MediaTek clock drivers and ChenYu enhanced the error path of mtk_clk_simple_probe and added mtk_clk_simple_remove. Let's use mtk_clk_simple_probe and mtk_clk_simple_probe in other MediaTek clock drivers as well. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the clock drivers for the entire clock tree of MediaTek Helio X10 MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen) and multimedia clocks (mmsys, mfg, vdecsys, vencsys). Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by:
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AngeloGioacchino Del Regno authored
The ref2usb_tx clock was introduced a long time ago and, at that time, the MediaTek clock drivers were using CLK_OF_DECLARE, so they would never unregister. Nowadays, unregistering clock drivers is a thing, as we're registering them as platform_driver and allowing them to be kernel modules: add a helper function to cleanup the ref2usb_tx clock during error handling and upon module removal. Signed-off-by:
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AngeloGioacchino Del Regno authored
In order to compile the clock drivers for various MediaTek SoCs as modules, it is necessary to export a few functions from the MediaTek specific clocks (and reset) libraries. Signed-off-by:
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AngeloGioacchino Del Regno authored
Remove an unneeded __init annotation from the declaration of function mtk_clk_register_ref2usb_tx(): this avoids section mismatch warnings during modpost phase when called from functions that have no such annotation (useful when clocks are platform drivers). Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the bindings for the clock drivers of the MediaTek Helio X10 MT6795 SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-5-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Add the reset controller bindings for MT6795. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the bindings for MT6795's clock controller. Signed-off-by:
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AngeloGioacchino Del Regno authored
Document the MediaTek Helio X10 (MT6795) bindings for the apmixedsys, infracfg, topckgen, pericfg and mmsys system controllers. Signed-off-by:
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- 01 Sep, 2022 4 commits
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AngeloGioacchino Del Regno authored
Add the reset idx for the t-phy port 1, used as either USB or PCI-Express (secondary controller) PHY, depending on board-specific configuration/layout. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the reset index for USBSIF P1 (T-PHY port 1), used as either USB or PCI-Express PHY reset. Signed-off-by:
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AngeloGioacchino Del Regno authored
The pwrmcu is responsible for power management and idle states in SSPM: on older SoCs this was managed in Linux drivers like sspm/mcupm/eemgpu but, at least on MT8195, this functionality was transferred to the ATF firmware. For this reason, turning off the pwrmcu related clocks from the kernel will lead to unability to resume the platform after suspend and other currently unknown PM related side-effects. Set the PWRMCU and PWRMCU_BUS_H clocks as critical to prevent the kernel from turning them off, fixing the aforementioned issue. Fixes: e2edf59d ("clk: mediatek: Add MT8195 infrastructure clock support") Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the reset idx for PCIe P0, P1, located in infra_ao RST2 registers. Signed-off-by:
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